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JPH0884161A |
PURPOSE: To provide a reception detecting circuit device for a serial communication equipment using a bi-phase code which can easily reduce the variation of operation performance, a current value to be consumed, size, etc. CONSTITUTION: ...
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JPH0877713A |
PURPOSE: To detect a specified frequency component in modulation data with a simple device structure by detecting a specified frequency component in modulation data by logically operating the modulation data and a binary signal and contr...
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JPH0879086A |
PURPOSE: To improve the processing speed of a gate circuit used for composing the code converter for converting an RBC signal into an SBC signal and to reduce the conversion time of the code converter. CONSTITUTION: The circuit is provid...
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JPH0879085A |
PURPOSE: To realize miniaturization, thin profile, low cost and circuit integration by eliminating the need for an output transformer. CONSTITUTION: The module is made up of an NRZ/RZ conversion circuit 1 converting a received NRZ signal...
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JPH0828061B2 |
Width restoring to eliminate unintended width variations in pulse width modulated data in combination with a phase lock loop allows pulse width modulated data in high density optical recordings. The width restoration is accomplished by d...
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JPH0828701B2 |
An improved NRZ clock and data recovery system lends itself to integration, includes a NRZ phase detector, an NRZ frequency detector and a lock detector, and provides automatic centering of the clock edge within the bit interval in a man...
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JPH0828679B2 |
A fiber optic digital data transmitting system is disclosed which has the capability of transmitting and accurately reproducing digital data signals at the receiver even when the optical signal is attenuated in the fiber optic transmitti...
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JPH0865167A |
PURPOSE: To obtain the PWM signal transmission method in which much more information is sent without extending the transmission time while keeping compatibility with a conventional system. CONSTITUTION: In the PWM transmission method in ...
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JPH0824311B2 |
A method is described for converting m-bit information words into n-bit code words and vice versa. The code words have a limited disparity in order to obtain a d.c. free code. A reduction of the lowfrequency content of the spectrum can b...
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JPH0817331B2 |
In a signal processing channel, digital values, corresponding to a digitized incoming analog signal representative of coded binary data, are processed. Using a state-dependent sequence detection algorithm appropriate functional expressio...
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JPH0851459A |
PURPOSE: To accurately detect information even from a received signal with a low S/N ratio by allowing the order of a sequence to be modulated to correspond to the symbol sequence of codes to be transmitted. CONSTITUTION: This transmitti...
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JPH0846526A |
PURPOSE: To obtain a DC free coding signal able to be detected by a detection circuit for class 4 of partial response. CONSTITUTION: A digital signal from an input terminal 1 is fed to a switch 2, where the signal is separated into two s...
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JPH0846525A |
PURPOSE: To improve the error rate of recovered data by comparing a sum between an equalization signal being an output of an identified point and a path metric difference corresponding to likelihood difference subject to one-bit delay wi...
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JPH08501429A |
PCT No. PCT/GB94/01478 Sec. 371 Date Mar. 6, 1995 Sec. 102(e) Date Mar. 6, 1995 PCT Filed Jul. 7, 1994 PCT Pub. No. WO95/02283 PCT Pub. Date Jan. 19, 1995A method of coding, and a coder, using a code in which data words are assigned to c...
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JPH0813020B2 |
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JPH0812988B2 |
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JPH0810808B2 |
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JPH088490B2 |
PURPOSE:To attain the normal operation of the circuit normally even at a high clock frequency, to attain the operation of the circuit at a fast speed with simple circuit constitution and to reduce the power consumption by providing plura...
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JPH088492B2 |
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JPH088491B2 |
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JPH083073Y2 |
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JPH088561B2 |
A CMI block synchronization circuit includes a clock deriving circuit, CMI decoding circuit, signal selection determining circuit and a selection circuit. In the clock deriving circuit, a clock CLKo having the same phase as a binary sign...
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JPH0818611A |
PURPOSE: To hardly erroneously synchronize with the generation characteristics of code errors and to improve the reliability of the detection of the code errors. CONSTITUTION: Transmission data inverted in an inverter 9 are converted to ...
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JPH084245B2 |
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JPH084226B2 |
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JPH084228B2 |
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JPH084227B2 |
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JPH084225B2 |
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JPH084229B2 |
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JPH084256B2 |
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JPH087492A |
PURPOSE: To provide an optical data recording/reproducing device dissolving failure due to the fact that the synchronizing data coincide with the encoding data. CONSTITUTION: The data recording/reproducing device 1 is constituted so as t...
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JPH088981A |
PURPOSE: To obtain a digital signal transmitter where a receiver hardly performs an erroneous decision due to the influence of noise even if a transmitter and the receiver are connected by a flat cable for a small wiring space. CONSTITUT...
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JPH082017B2 |
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JPH07123226B2 |
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JPH07336227A |
PURPOSE: To provide a D/A converter by which a resolution equal to that of a conventional D/A converter is obtained with small number of components than that of the conventional D/A converter processing basically a binary number. tie CON...
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JPH07120952B2 |
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JPH07120951B2 |
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JPH07121019B2 |
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JPH07118653B2 |
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JPH07118657B2 |
A binary data encoding process comprises the steps of separating a given binary data sequence at every two bits by a serial/parallel shift register (18), and converting the separated 2-bit data into a 3-bit code by using a logic circuit ...
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JPH07118654B2 |
An arithmetic unit having true and false deciding circuits (21 to 24) for receiving a first input signal A and a second input signal B to output the second input signal or complement of the same in response to the sign (most significant ...
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JPH07114418B2 |
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JPH0753318Y2 |
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JPH07112157B2 |
A decoder for Manchester encoded data in which the . encoded data (MCIN) is sampled by a clock signal (CLK) to produce a decoded data signal (NRZD). The decoded data is combined with a delayed version (MCDEL) of the encoded data, to prod...
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JPH07105789B2 |
A transmission control circuit for use in a data terminal equipment receiver section is disclosed. The output of a phase locked loop or narrow band tuned filter input register clocking circuit which includes a quasi-differentiator and fu...
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JPH07105728B2 |
A system for transmitting digital information including a coding arrangement, a transfer medium, for example a record carrier, and a decoding arrangement. In the coding arrangement the digital information is received as groups of input w...
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JPH07105725B2 |
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JPH0749871Y2 |
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JPH07288931A |
PURPOSE: To enable high-speed and high-accuracy forecasting, in the case of forecasting future time series data from past time series data. CONSTITUTION: This device is composed of a coefficient setter 5, which regularizes past time seri...
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JPH07283838A |
PURPOSE: To demodulate a signal while eliminating the effect of noise and distortion produced in the transmission system by modulating digital information to be sent at a period of a carrier to narrower a spread of a spectrum to be very ...
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