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JPH0799808B2 |
An arithmetic and logic unit control circuit includes arithmetic circuits (10a-10d) for generating the absolute value ¦A¦ of an input signal A and the complement &upbar& B of an input signal B from n-bit input signals A and B in respon...
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JPH0797750B2 |
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JPH0797751B2 |
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JPH07264250A |
PURPOSE: To transmit serial data by allowing a transmission controller not having an oscillating source to superimpose data onto a clock signal from a transmission controller having an oscillation source and taking the operating timing w...
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JPH0795756B2 |
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JPH0793561B2 |
A circuit for converting tri-state signals into binary signals comprises two current sources, each of which is connected to a common input via a respective diode path and to a respective output transistor via a further respective diode p...
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JPH0789617B2 |
For encoding a stream of k-bit data bytes into a stream of m-bit code bytes satisfying given constraints, a coding principle and coder apparatus are disclosed which allow pipelined and parallel handling of the byte stream. Each data byte...
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JPH07248340A |
PURPOSE: To accurately detect an average level even when an AC signal changes with the lapse of time and output time is short. CONSTITUTION: An AC signal 1 is inputted to a detecting circuit 2, and a detecting signal 3 being an envelope ...
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JPH0787381B2 |
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JPH0787380B2 |
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JPH0786513B2 |
A reference voltage generating circuit (9) for supplying a reference voltage (Vag+/- DELTA V) is connected to a peak hold or tracking circuit (34). The setting value of the voltage ( DELTA V) is determined to a value exceeding the minute...
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JPH0787379B2 |
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JPH07240720A |
PURPOSE: To obtain an effective and simple binary coder. CONSTITUTION: An encoder logic 400 consists of one finitestate machine, and this finite-state machine receives a present state 403 and an input bit 401 and outputs 0 or more output...
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JPH0783386B2 |
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JPH0777386B2 |
PURPOSE:To realize the low power consumption by turning on an optical signal by the pulse of extremely narrow width synchronizing with the level variation of a binary input signal. CONSTITUTION:A transmitter 10 is provided a modulating c...
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JPH0735475Y2 |
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JPH0775357B2 |
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JPH0775323B2 |
PCT No. PCT/GB86/00127 Sec. 371 Date Dec. 11, 1986 Sec. 102(e) Date Dec. 11, 1986 PCT Filed Mar. 6, 1986 PCT Pub. No. WO86/05342 PCT Pub. Date Sep. 12, 1986.A method and system for demultiplexing an optical signal having a bit rate in th...
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JPH0773286B2 |
Data communication system between computers; communication paths composed of m transmission lines are formed between two computers, and data to be transferred are coded based on a coding table comprised of encoding codes. When transmitti...
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JPH0771007B2 |
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JPH0771006B2 |
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JPH07183849A |
PURPOSE: To provide an optical space transmitter of a simple constitution enabling the transmission of an optical signal which is difficult to be affected by the optical noise component in interior environments. CONSTITUTION: A transmitt...
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JPH07182791A |
PURPOSE: To facilitate the decoder of an operation mode by programming one of the output stream of the single bit of decoded data and the dual bit output stream of the decoded data. CONSTITUTION: The second re-timed output signals of a f...
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JPH0766479B2 |
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JPH07176138A |
PURPOSE: To prevent the generation of errors by the transmission delay of signals by storing bits finally processed in a second combinational logic network (RC1) in a shift register, predicting the time when (n) bits are process in a fir...
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JPH07169199A |
PURPOSE: To provide the class of coding capable of selecting an optimum coding system depending on a desired use. CONSTITUTION: This recording carrier carries the signals of a group of code word strings. Respective cord words are compose...
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JPH0761068B2 |
A method for data window centering in a multifrequency data separator (12) based on having the frequency of a voltage-controlled oscillator (20) at least twice that of read data window frequency, and setting delay of a delay line (14) us...
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JPH0761066B2 |
A data separator produces a reference clock from encoded data through the use of a digital logic that simulates the operation of an analog phase-locked loop. The digital phase-locked loop includes a counter oscillator that develops a per...
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JPH0754914B2 |
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JPH0754912B2 |
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JPH07147536A |
PURPOSE: To constitute a multilevel logic circuit by using a multi-peak type resonance tunneling device by making the binary work of an L-value show the same numeric value as that of a range N when that of the range N is impressed at the...
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JPH07147543A |
PURPOSE: To obtain the circuit capable of being highly integrated at a low cost by checking production of a non-transition bit cell period after the transition at all times and extracting a data clock speed from a border cell, thereby de...
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JPH0752846B2 |
A method for rapidly recovering the clock from Manchester-encoded signals using simple digital techniques is provided for use in an inexpensive Manchester-encoding receiver. The received Manchester-encoded signal is monitored to determin...
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JPH07143108A |
PURPOSE: To minimize the scale of the hardware relating to communication of digital information. CONSTITUTION: In the data communication circuit provided with a slave set 3, a master set 2 and a 2-wire bus 6, the master set 2 provides po...
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JPH0746799B2 |
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JPH0746480B2 |
A process for the base band modulation of a data signal on a magnetic support is characterized in that: (a) a bit value of 0 is marked if it follows an unmarked bit of value of 0 or a sequence of three consecutive unmarked bits of value ...
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JPH0746479B2 |
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JPH0746481B2 |
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JPH0746478B2 |
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JPH0746413B2 |
For the purpose of increasing storage density of data recorded on a magnetic recording medium, particularly on a magnetic tape, a coder stage is supplied with data signals allocated to the record data and with high-frequency magnetizatio...
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JPH0744570B2 |
A method and apparatus for transmission of digital data in which data words having M parallel bits are encoded into code words having N parallel bits, the code words being serially transmitted and being accompanied by flags such as Start...
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JPH07123007A |
PURPOSE: To reduce waveform distortion on a bus of an inductive load by forming 1st binary data with a code representing nearly equal power to a positive and a negative pulse and forming 2nd binary data with a code representing an amplit...
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JPH0738245B2 |
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JPH0738244B2 |
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JPH0786953A |
PURPOSE: To input four ways of signal inputs from one input terminal with simple configuration by fetching and holding an input signal previously synchronized with the edges of rise and fall a clock pulse. CONSTITUTION: The clock pulse i...
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JPH0724382B2 |
In recording systems using partial-response maximum-likelihood detection (PRML) techniques, data sequences are preceded by a preamble consisting of all ones. Coding schemes are disclosed which allow to keep the number of consecutive ones...
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JPH0767140A |
PURPOSE: To prevent a code word disadvantageous for the extraction or identificial reproduction of a clock from being allocated to a code word for video data by adopting a specified generating polynomial. CONSTITUTION: A signal B(X) prov...
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JPH0766731A |
PURPOSE: To make it possible to automatically recover, synchronism when step-out occurs by adjusting the synchronism by using the falling timing of a CMI code as a trigger. CONSTITUTION: A CMI code signal inputted from a CMI code input t...
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JPH0721942B2 |
A method of reducing DC components in a digital information signal comprised of a plurality of 8-bit data words by converting each of the 8-bit data words to a 10-bit data word, comprises the steps of: selecting the 10-bit data words hav...
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JPH0750690A |
PURPOSE: To facilitate the switching of systems for the balanced type and the unbalanced type of interface conditions by detecting the signal level of a ground- side when the feature impedance of an input transmission line is converted i...
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