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JPS63287207A |
PURPOSE: To reduce the circuit element by connecting plural storage means to a 1st storage means. CONSTITUTION: When a signal with chattering is inputted to an input terminal 1, a master latch 3 is in the through state with a clock signa...
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JPS63286936A |
PURPOSE: To reduce a hard quantity in a master-slave type register, which can hold plural data by using a means to make a master part common to respective fields. CONSTITUTION: A continuous clock is supplied to , and the clocks which hav...
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JPS63263924A |
PURPOSE: To attain a simple constitution to the hardware by using the least significant bit of a shift register set to logic '0' as a start bit and a period of logic '1' without a clock active pulse as a stop bit. CONSTITUTION: Parallel ...
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JPS63260242A |
PURPOSE: To eliminate the need for a reset signal from a microcomputer by sending a data from the microcomputer with bit constitution more than a data bit number by one bit. CONSTITUTION: Inverted 8-bit data 0∼7 are consecutive in a da...
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JPS6354251B2 |
PURPOSE:To fetch easily a parallel binary data by one signal line by using as an input signal a ternary series signal which assigns a binary data by one bit each in front of a prescribed number of index signals. CONSTITUTION:When a terna...
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JPS63257346A |
PURPOSE: To switch the line between an active line and a standby line uninterruptibly by using an output of active synchronization and an output of a standby synchronization so as to start an active frequency divider and a standby freque...
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JPS6352494B2 |
The logic circuit has cascade-connected flip-flops A, B, C and D. The data inputs DA, DB, DC and DD to the flip-flops have gate arrangements GA, GB, GC and GD connected to them. The circuit receives either a shift signal SHT or a count s...
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JPS63248281A |
PURPOSE:To output a page synchronizing signal, an image synchronizing signal and a serial image signal synchronizing with the synchronizing signals by converting parallel image data to serial image data, synchronizing with a clock signal...
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JPS63242037A |
PURPOSE: To contrive the improvement of the reliability of data transmission by stopping a check data in sending a serial data having an error so as to handle it as a conversion error of a reception data. CONSTITUTION: Even when a PS con...
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JPS63242029A |
PURPOSE: To receive a serial data while converting it into a parallel data vary simply at high speed by fetching a data by means of a clock multiplexed in a serial data. CONSTITUTION: In obtaining an output A in the unit of bytes from a ...
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JPS63232627A |
PURPOSE: To convert stably data at a high speed by ANDing a clock signal of 4-series parallel data and a 2-multiple clock signal by a 1st 2-multiple means by means of an AND means so as to use the signal as a trigger pulse of a 4-bit shi...
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JPS63228833A |
PURPOSE: To eliminate the redundancy of the hardware of a parallel/serial converting part by producing the timing via an external ROM and applying the control signals to all channels independently of each other. CONSTITUTION: A ROM 10 pr...
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JPS6347373B2 |
PURPOSE:To facilitate timing control of data transfer by accessing one bit in a data buffer through the selection of a buffer address and a bit address for attaining data conversion. CONSTITUTION:When a buffer address selecting circuit 1...
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JPS63226068A |
PURPOSE: To convert plural serial input signals easily in parallel through a circuit element designed into one chip and therefore realize a simultaneous output by a method wherein a horizontal CCD and a vertical charge transferring secti...
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JPS6347014B2 |
A parallel-serial converter comprises a plurality of selection-delay unit circuits. The unit circuit selectively receives an output signal from the immediately preceding unit circuit and one of a plurality of input parallel signals and s...
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JPS63226121A |
PURPOSE: To attain serial/parallel conversion for an auxiliary data signal or the like in a transmission line system by providing a frequency division circuit whose reset pulse is formed by a clock synchronously with a parallel data. CON...
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JPS63221717A |
PURPOSE: To convert a serial signal into a parallel signal and to fetch the signal into a microprocessor efficiently by latching the serial signal in parallel via AND gates opened sequentially. CONSTITUTION: The S/P conversion circuit is...
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JPS63138659U |
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JPS6334386Y2 |
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JPS63215053A |
PURPOSE: To reduce the wiring area of a semiconductor integrated circuit, by applying a serial transmission to the data transmission in a semiconductor integrated circuit. CONSTITUTION: In the vicinity of the input pad of a semiconductor...
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JPS6343930B2 |
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JPS63194422A |
PURPOSE: To make the provision of a counter unnecessary, by providing an FF which inverts and holds the least significant bit of a parallel data, detecting the completion of a conversion operation by the propagation of the above n-bit va...
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JPS6339938B2 |
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JPS6337411B2 |
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JPS63176021A |
PURPOSE: To simplify a testing device by constituting an M-series generator in a way that a selector is connected to the input of a shift register, the selector is switched by a switching input and the output of an arithmetic circuit is ...
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JPS63169128A |
PURPOSE: To constitute the titled circuit with lease circuit elements by constituting the titled circuit with a signal selection circuit and an output holding circuit instead of a shift register to hold a parallel data. CONSTITUTION: The...
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JPS63108238U |
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JPS6333176B2 |
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JPS63158916A |
PURPOSE: To prevent the expansion of a circuit constitution scale, by inputting a load pulse to cascade-connected shift registers of four bits and eight bits via a multiplexing gate, storing parallel inputs in the shift registers respect...
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JPS6332292B2 |
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JPS6330820B2 |
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JPS63141415A |
PURPOSE: To facilitate the programming by outputting a load pulse from a comparator when a time set in a 1st register and a value of a timer are coincident to apply parallel serial conversion to a parallel data written in a 2nd register....
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JPS6319860Y2 |
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JPS63128818A |
PURPOSE: To facilitate large scale integration by controlling the storage of a serial data into a buffer group via a timing generating circuit comprising shift registers and outputting sequentially a column buffer output via a correspond...
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JPS6326897B2 |
A serial-parallel converter for storing sequentially a serially input digital signal in a predetermined number of elements and producing the stored data at one time as a parallelly output digital signal. The serially input digital signal...
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JPS6326930B2 |
A serial-to-parallel converter receives serial data bits forming serial input words and serial word synchronizing pulses indicating the length of the serial input words. A parallel clock signal is generated synchronously with an integer ...
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JPS63117520A |
(57) [Abstract] Since this gazette is application data in front of an electronic application, the data of an abstract is not recorded.
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JPS6372605U |
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JPS63103521A |
PURPOSE: To devise the titled circuit in such a way that the switching timing from the parallel operation into the serial operation is not overlapped onto the shift timing by using four NOR gates in an IC in an inexpensive way. CONSTITUT...
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JPS6397017A |
PURPOSE: To convert serial data having optional number of bits into parallel data at high speed by outputting the parallel data at the time of counting burst clock pulses by the number according to the number of bits of the serial data. ...
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JPS6361838U |
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JPS6318908B2 |
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JPS6388635A |
A programmable FIFO buffer is disclosed which including a (serial) input register for receiving signals representing in serial format a word of data and for developing signals representing the data word converted to parallel format, a co...
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JPS6379442A |
PURPOSE: To allow the titled system to cope with diversified general applications with simple constitution by using an output of a shift register and a counter of constant level cyclic type so as to control the data input to a memory. CO...
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JPS6370667A |
PURPOSE:To contrive to simplify the constitution of a parallel data circuit by inputting one of two kinds of data sequence before conversion selectively to a data converting means and composing parallel data of the specific number of bit...
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JPS6369327A |
PURPOSE: To attain normal conversion where a frequency division clock and a parallel data are synchronized by giving a frequency division clock phase- shifted by an output clock to a parallel/serial conversion means. CONSTITUTION: An n-s...
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JPS6365721A |
PURPOSE: To decrease the circuit scale of the titled parallel expansion circuit for parallel processing by inserting flag information representing the channel order number to each parallel data, converting the data serially, sending the ...
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JPS6359118A |
PURPOSE: To attain the small scale of the circuit and the reduction in number of components by receiving a count signal as an address signal and outputting a stored data to a signal selection means, a serial signal converting means and a...
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JPS6358674A |
PURPOSE:To follow a high-speed input signal by calculating in parallel the discrete cumulative values of input signals and performing a magnetic recording/ coding job. CONSTITUTION:The input signals supplied from an input signal source 1...
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JPS635927B2 |
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