Title:
【発明の名称】MOS型半導体装置
Document Type and Number:
Japanese Patent JP2695014
Kind Code:
B2
Abstract:
A MOS type semiconductor device and a method for the manufacture of the same are disclosed in which a gate electrode (16) is so formed over a semiconductor substrate (11) of a first conductivity type with a gate insulating film (12) formed therebetween as to provide a three-layered structure composed of a first high melting point metal silicide layer (13) formed on the gate insulating film (12), high melting point metal layer (14) formed on the first high melting point metal silicide (13) and a second high melting point metal silicide layer (15) formed on the high melting point metal layer (14). In the gate electrode (16), a length of the first high melting point silicide layer (13) defined in the same direction as that in which a channel region extends is made smaller in length than the high melting point metal layer (14).
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Inventors:
Koji Murakami
Matsunaga Taira
Matsunaga Taira
Application Number:
JP23064289A
Publication Date:
December 24, 1997
Filing Date:
September 06, 1989
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/768; H01L21/28; H01L23/522; H01L29/423; H01L29/49; H01L29/78; (IPC1-7): H01L29/78
Domestic Patent References:
| JP62105473A | ||||
| JP5984472A | ||||
| JP61134072A | ||||
| JP63296280A | ||||
| JP6221558U |
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)