キャッシュ/メインメモリのコンシステンシを維持するための装置及び方法

Japanese Patent JP3637054

B2

An apparatus and method for maintaining cache/main memory consistency in a data processing system including a write-through cache (14). For write operations of less than a word in length, the write data stored within a FIFO memory device 18 associated with a first bus agent reflects the result of a read/modify/write type of access wherein a byte or half word has been merged by a local processor 12 with a cache word. Memory control lines driven to a system bus 20 indicate to a memory controller 22 that a write operation is to be accomplished as a word write, thereby eliminating the additional time required to achieve a read/modify/write memory controller cycle. To prevent the occurrence of a problem wherein another bus agent, such as another CPU or an I/O device, writes to a system memory 24 during an interval of time that the word of data is temporarily buffered within the FIFO there is provided circuitry for detecting an external write made to the system memory. Circuitry is provided for changing the memory command lines to indicate, instead of a word write, a byte write or a half-word write operation. This causes the memory controller to operate only upon the portion of data word that was modified by the local processor and to perform a conventional read/modify/write type of cycle to merge the byte or half word with a word from main memory.

JP2008310465	SEMICONDUCTOR DEVICE
JP2011065503	CACHE MEMORY SYSTEM AND CONTROL METHOD FOR WAY PREDICTION OF CACHE MEMORY
WO/2013/062542	SEGMENTED CACHES

Patel, Biko Jay

JP50746590A

April 06, 2005

March 28, 1990

Click for automatic bibliography generation  

LG Electronics Incorporated

G06F12/08; (IPC1-7): G06F12/08

Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Otsuka Sumie

Previous Patent: MAGNETIC RECORDING MEDIUM, ITS MANUFACTURING METHOD, AND MAGNETIC RECORDING DEVICE

Next Patent: 光保護フィルターとしてのベンズイミダゾール誘導体の使用