Title:
集積回路の試験
Document Type and Number:
Japanese Patent JP4579230
Kind Code:
B2
Abstract:
An integrated circuit with a test interface contains a boundary scan chain with cells ( 14 ) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell ( 14 ) is also coupled between a respective one of the terminals ( 16 ) and the core circuit ( 10 ). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells ( 14 ) transport data serially along the boundary scan chain while selectable second ones of the cells ( 14 ) write or read data that has been or will be transported through the first ones of the cells ( 14 ) in the further mode to or from the terminals ( 16 ) from or to the scan chain.
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Inventors:
Leon, M.A.Fan, De, Loft
Thomas, F. Baryer's
Frank, Fan, Dell, Hayden
Thomas, F. Baryer's
Frank, Fan, Dell, Hayden
Application Number:
JP2006502546A
Publication Date:
November 10, 2010
Filing Date:
January 28, 2004
Export Citation:
Assignee:
NXP B.V.
International Classes:
G01R31/28; G01R31/3185; H01L21/822; H01L27/04
Domestic Patent References:
| JP3252569A | ||||
| JP7087161A | ||||
| JP10019983A | ||||
| JP10090369A | ||||
| JP2002311107A | ||||
| JP2003004818A | ||||
| JP2003121497A |
Other References:
VRANKEN H., et al.,Enhanced Reduced Pin-Count Test for Full-Scan Design,ITC INTERNATIONAL TEST CONFERENCE,米国,IEEE,2001年10月30日,pp. 738-747
VERMEULEN, B., et al.,IEEE 1149.1-compliant Access Architecture for Multiple Core Debug on Digital System Chip,INTERNATIONAL TEST CONFERENCE,米国,IEEE,2002年10月 7日,pp. 55-63
VERMEULEN, B., et al.,IEEE 1149.1-compliant Access Architecture for Multiple Core Debug on Digital System Chip,INTERNATIONAL TEST CONFERENCE,米国,IEEE,2002年10月 7日,pp. 55-63
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Takeshi Sekine
Takahashi
Hidetoshi Tachibana
Takeshi Sekine
Takahashi