Title:
薄膜半導体装置及び薄膜半導体装置を含む画像表示装置
Document Type and Number:
Japanese Patent JP4744700
Kind Code:
B2
Abstract:
In an MIS field effect transistor having a gate electrode (18) formed on a first semiconductor layer which is a polycrystalline silicon film on an insulating substrate (100) through a gate insulating film (17), a channel region (12) formed in the semiconductor layer and a source region (20) and a drain region (19) arranged on both sides of the channel region (12), a thin film semiconductor device has a main orientation of at least the channel region of ä110ü with respect to the surface of the gate insulating film. Further, a polycrystalline semiconductor film having a main orientation of the surface almost perpendicular to a direction for connecting the source (20) and drain (19) regions of ä100ü is preferably used in the channel (12) of a semiconductor device. According to the present invention, a semiconductor device having a high-quality polycrystalline semiconductor film whose grain boundary, grain size and crystal orientation can be controlled and whose film roughness and crystal defects formed by crystallization have been reduced can be obtained on the insulating substrate (100).
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Inventors:
Mutsuko Hatano
Shinya Yamaguchi
Yoshinobu Kimura
Park
Shinya Yamaguchi
Yoshinobu Kimura
Park
Application Number:
JP2001019570A
Publication Date:
August 10, 2011
Filing Date:
January 29, 2001
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L21/336; H01L29/786; C30B1/00; H01L21/00; H01L21/20; H01L21/26; H01L21/324; H01L21/36; H01L21/42; H01L21/44; H01L21/4763; H01L21/477; H01L21/84; H01L23/62; H01L27/01; H01L27/12; H01L31/0328; H01L31/0336; H01L31/0392; H01L31/072; H01L31/109
Domestic Patent References:
| JP11040815A | ||||
| JP60091622A | ||||
| JP64050569A | ||||
| JP64059807A |
Attorney, Agent or Firm:
Polaire Patent Business Corporation
Katsuo Ogawa
Kyosuke Tanaka
Takashi Sasaki
Katsuo Ogawa
Kyosuke Tanaka
Takashi Sasaki