強誘電体メモリ - Seiko Epson Corporation

Title:

強誘電体メモリ

Document Type and Number:

Japanese Patent JP5051344

Kind Code:

B2

Abstract:

To suppress degradation in the characteristics of a ferroelectric memory under utilization environments or during manufacturing processes of the ferroelectric memory.

The ferroelectric memory comprises a semiconductor substrate 10; a transistor formed on the semiconductor substrate 10; a capacitor 50 formed on the upper part of the semiconductor substrate 10 and includes a first electrode 54, a first ferroelectric layer 56 formed on the first electrode 54, and a second electrode 58 formed on the first ferroelectric layer 56; and a laminated barrier layer 60 formed so as to coat the capacitor 50 and having a first insulating layer, a second ferroelectric layer formed on the first insulating layer, and a second insulating layer formed on the second ferroelectric layer.

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Inventors:

Kenichi Kurokawa

Application Number:

JP2006216042A

Publication Date:

October 17, 2012

Filing Date:

August 08, 2006

Export Citation:

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Assignee:

Seiko Epson Corporation

International Classes:

H01L21/8246; H01L27/105

Domestic Patent References:

JP2002110937A
JP11126883A
JP2006049795A
JP7273297A

Foreign References:

WO2006011196A1

Attorney, Agent or Firm:

Yukio Fuse
Mitsue Obuchi

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