Title:
DC-DCコンバータのラッチアップ防止回路
Document Type and Number:
Japanese Patent JP5334359
Kind Code:
B2
Abstract:
There is provided a circuit for preventing latch-up in a DC-DC. The circuit for preventing a latch-up phenomenon in a DC-DC converter, the DC-DC converter having a first and a second DC-DC converters coupled with each other in one chip for receiving an input voltage to generate a positive voltage and a negative voltage, respectively, in which a parasitic block with a PNP transistor and an NPN transistor causing a latch-up phenomenon is embedded, the circuit includes a first pathway for controlling an input current flowing to the first DC-DC converter from an input terminal receiving the input voltage in order that the PNP transistor is turned on and the NPN transistor is not turned on; and a second pathway for supplying the input current to the first DC-DC converter intactly at a timing that both the positive and negative voltages reach target voltages.
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Inventors:
Lee Tadung
Application Number:
JP2005372917A
Publication Date:
November 06, 2013
Filing Date:
December 26, 2005
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
H01L21/822; H01L27/04; H01L27/06; H02M3/00; H03K17/08
Domestic Patent References:
| JP3112157A |
Attorney, Agent or Firm:
Patent Business Corporation Saegusa International Patent Office