Title:
金属ブロックと接合パッド構造
Document Type and Number:
Japanese Patent JP6429209
Kind Code:
B2
Abstract:
In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.
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Inventors:
What
Roh Hikoike
Hong Feng
Shun Sung
Yang Atsushi
Roh Hikoike
Hong Feng
Shun Sung
Yang Atsushi
Application Number:
JP2017013157A
Publication Date:
November 28, 2018
Filing Date:
January 27, 2017
Export Citation:
Assignee:
Taiwan Semiconductor Manufacturing Company,Ltd.
International Classes:
H01L25/065; H01L21/3205; H01L21/768; H01L23/522; H01L25/07; H01L25/18; H01L27/146
Domestic Patent References:
| JP4171923A | ||||
| JP4093020A | ||||
| JP2251139A | ||||
| JP2012033894A | ||||
| JP2012164870A | ||||
| JP2015128187A | ||||
| JP2011204915A | ||||
| JP2000269473A | ||||
| JP2012064709A | ||||
| JP2013058661A | ||||
| JP2013187360A |
Foreign References:
| WO2016152577A1 | ||||
| WO2013115075A1 |
Attorney, Agent or Firm:
Hideaki Tazawa
Hamada Hatsune
Nakashima Shigeru
Tatsuya Sakamoto
Tsujioka Masaaki
Kazuma Inoue
Hamada Hatsune
Nakashima Shigeru
Tatsuya Sakamoto
Tsujioka Masaaki
Kazuma Inoue