PURPOSE: To reduce the number of logic elements by configurating a 1/3 frequency divider circuit with three D FFs, one buffer, one inverter and one AND gate.

CONSTITUTION: When the output of each Q terminal of D FFs 1-3 is 0, the output of an AND gate 4 goes to logic '1'. When an input signal 21 is increased, the signal is inputted to the terminal C of the FF 2 via a buffer 6 and the output signal of the terminal Q of the FF2 is changed to '0'. When the input signal 21 is decreased, an output signal 22 via an inverter 5 is inputted to the terminal C of the FF1, the output of the terminal inverse of Q remains logic '1' and the output signal 25 of the gate 4 remains logic '0'. When the input signal 21 is increased, since an output signal at the terminal D of the FF2 just before the increase is logic '0', the output signal at the terminal inverse of Q goes to '1' and the output signal 25 of the AND gate 4 also goes to '1' and an output signal at the terminal inverse of Q of the FF3 goes to '1'.