Title:
再配置可能な論理環境で使用するための効率的な高性能データ動作エレメント
Document Type and Number:
Japanese Patent JP2004531149
Kind Code:
A
Abstract:
A reconfigurable chip is described using a reconfigurable functional unit including a shifter unit, arithmetic logic unit and multiplexers. The data path units are interconnected to other data path units. The interconnection is preferably done by transferring word length data. The shifter allows for the word length data to be adjusted for use in the arithmetic logic unit. In a preferred embodiment the reconfigurable functional units are controlled by reconfigurable functional unit instructions. The reconfigurable functional unit instructions preferably are stored in a reconfigurable functional unit instruction memory which is addressed by a state machine on the chip.
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Inventors:
Lindner, Joshua
Rye,gary
Lamb, peter
Rollins, mark, edward
Dinkevich, Vladimir
Greenberg, Craig, Bradley
Philips, Christopher, Yee
Wang, Shin
Taylor, bradley, ell
Rye,gary
Lamb, peter
Rollins, mark, edward
Dinkevich, Vladimir
Greenberg, Craig, Bradley
Philips, Christopher, Yee
Wang, Shin
Taylor, bradley, ell
Application Number:
JP2003505770A
Publication Date:
October 07, 2004
Filing Date:
May 02, 2002
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
H01L21/82; G06F9/318; G06F9/38; G06F15/78; H03K19/173; (IPC1-7): H03K19/173; H01L21/82
Attorney, Agent or Firm:
Masanori Honjo
Yoshiko Honjo
Yoshiko Honjo