Title:
ELECTRONIC CIRCUIT
Document Type and Number:
Japanese Patent JPH03166804
Kind Code:
A
Abstract:
PURPOSE: To remove a beat frequency by using a 1st switch capacitor circuit as an input to a 1st amplifier of an FM detector and a 2nd switch capacitor circuit as a feedback element of a 2nd amplifier. CONSTITUTION: An FM detector 100 consists of a frequency-voltage converter 101, a compensating circuit 103 and a clock signal source 105. In the converter 101, a voltage at the reverse input of an operational amplifier 124 varies in response to the variation of apparent resistance of switching capacitor circuits 10 and 12. The output of the converter 101, therefore, varies in response to variation of the resistance. When an IF signal is inputted to the circuits 10 and 12, an undesirable offset voltage is generated in an output of the operational amplifier 124 and the succeeding circuit. The roles of the circuits 10 and 12 and a feedback resistor 127 are inverted in a circuit 103 by switch capacitor feedback circuits 14 and 16, etc. Further, electric separation between the circuits 10 and 12 and circuits 14 and 16 of the circuit 103 prevents a disturbing beat frequency from being generated.
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Inventors:
RICHIYAADO EI KENEDEII
SEIDO AARU ZARABADEI
SEIDO AARU ZARABADEI
Application Number:
JP22788490A
Publication Date:
July 18, 1991
Filing Date:
August 29, 1990
Export Citation:
Assignee:
DELCO ELECTRONICS CORP
International Classes:
H03H19/00; H03D3/00; (IPC1-7): H03D3/00; H03H19/00
Domestic Patent References:
| JPS5249710A | 1977-04-21 | |||
| JPS6156501A | 1986-03-22 |
Attorney, Agent or Firm:
Kyozo Yuasa (4 outside)