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Title:
ERRONEOUS WRITING PREVENTING CIRCUIT
Document Type and Number:
Japanese Patent JPH0536290
Kind Code:
A
Abstract:

PURPOSE: To prevent the erroneous writing at the time of programming an ultraviolet ray erasing type EP-ROM.

CONSTITUTION: A differential amplifier is constituted of P channels MOSFET 24 and 25 and N channels MOSFET 22, 23 and 26 and the reference voltage of the differential amplifier provides resistors 27 and 28 and is generated. As the input signal of the differential amplifier, a digit line is connected. An output F of the differential amplifier is inputted to a NAND circuit 29 to input a writing external signal PGM and the output of the NAND circuit 29 is inputted to an inverter 30. The output of the inverter 30 becomes the voltage control signal of a word line. Thus, the reference voltage generation by the resistor is performed, the circuit to perform the discharging of the digit line up to the reference voltage is provided and thus, there is the effect that the erroneous writing to the memory cell at the time of programming is eliminated.


Inventors:
NAKAJIMA YASUHIRO
Application Number:
JP19334691A
Publication Date:
February 12, 1993
Filing Date:
August 02, 1991
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C16/02; G11C16/06; G11C17/00; (IPC1-7): G11C16/06
Domestic Patent References:
JP3005299U1994-12-13
Attorney, Agent or Firm:
Uchihara Shin