Title:
ETCHING METHOD FOR SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3295899
Kind Code:
B2
Abstract:
PURPOSE: To suitably suppress the irregularity of the etching depth even without regulating the composition of semiconductor layers and a film structure in a semiconductor substrate required for selective etching the semiconductor layers made of a plurality of layers.
CONSTITUTION: A resist pattern 4 having an opening 5 for etching is first formed on the surfaces of two different types of semiconductor layers, i.e., first and second semiconductor layers 2 and 3 laminated on a semiconductor substrate 1. The second layer 3 of the upper layer is etched from the opening 5 of the pattern 4 formed in this manner to the surface of the first layer 2 of the lower layer. Further, thereafter, the surface oxide film 21 formed on the surface of the layer 2 of the lower layer exposed by the etching is selectively etched. Or, the surface of the layer 2 of the lower layer exposed by the previous etching is separately oxidized, and in the later etching, the surface oxide film 21 formed by the oxidizing is selectively removed.
More Like This:
Inventors:
Koichi Hoshino
Takuya Takatani
Yoshiki Ueno
Takuya Takatani
Yoshiki Ueno
Application Number:
JP14787195A
Publication Date:
June 24, 2002
Filing Date:
June 14, 1995
Export Citation:
Assignee:
株式会社デンソー
科学技術振興事業団
科学技術振興事業団
International Classes:
H01L29/41; H01L21/306; H01L21/335; H01L21/338; H01L29/778; H01L29/812; (IPC1-7): H01L21/338; H01L29/778; H01L29/812
Domestic Patent References:
| JP677255A | ||||
| JP77004A |
Attorney, Agent or Firm:
Hironobu Onda