Title:
フィードフォワード双方向注入されたスプリットゲートフラッシュメモリセル
Document Type and Number:
Japanese Patent JP6974684
Kind Code:
B2
Abstract:
A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second floating gate (FG) are on the semiconductor surface. A common source or common drain is between the first and second FG. A first select gate and a second select gate on a select gate dielectric layer is between a first BL source or drain (S/D) and the first FG and between a second BL S/D and the second FG, respectively. The first select gate has a first pocket region that has a first doping distribution different from a second doping distribution in a second pocket region associated with the second select gate which reduces a variation in read current (Ir) for the cell between measuring Ir using the first select gate and measuring Ir using the second select gate.
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Inventors:
Shan gen bo
Douglas Todd Glider
Douglas Todd Glider
Application Number:
JP2017550145A
Publication Date:
December 01, 2021
Filing Date:
March 24, 2016
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
H01L21/336; H01L27/11524; H01L29/788; H01L29/792
Domestic Patent References:
| JP2012109390A | ||||
| JP3003274A | ||||
| JP2003218212A | ||||
| JP2001308317A | ||||
| JP10326494A |
Other References:
AKIL, Nader et al.,Optimization of Embedded Compact Nonvolatile Memories for Sub-100-nm CMOS Generations,IEEE Transactions on Electron Devices,2005年04月,Vol. 52, No. 4,p.492 - 499
Attorney, Agent or Firm:
Kyozo Katayose