Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
INSULATED GATE FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH0637304
Kind Code:
A
Abstract:

PURPOSE: To reduce the intensity of an electric field near the drain of an insulated gate field effect transistor (FET) by using a gate film having a uniform thickness.

CONSTITUTION: A drain region 2 and a source region 3 are formed on respective sides of a channel region 9 formed on the top surface of a semiconductor substrate 1. A gate insulating film 3 is formed on the channel region 9. A gate electrode 6 and a floating electrode 7 are provided on the gate insulating film 3. The gate electrode 6 lies above the channel region 9 closer to the source region 3, but excluding the area near the drain region 2, and the floating electrode 7 lies above the channel region 9 near the drain region 2. This insulated gate FET further has a dielectric film 4, formed on the substrate 1 and covering the gate and floating electrodes 6 and 7, and a coupling electrode 8, formed on the dielectric film 4. The electrode 8, made of a conductor, partially overlies the gate and floating electrodes 6 and 7.


Inventors:
WARASHINA TAKU
Application Number:
JP18977692A
Publication Date:
February 10, 1994
Filing Date:
July 17, 1992
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
H01L29/78; (IPC1-7): H01L29/784
Attorney, Agent or Firm:
Teiichi