Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP6937864
Kind Code:
B2
Abstract:
To provide a semiconductor device having a vertical structure with stable withstand voltage characteristics, low off loss due to reduction of a leakage current at the time of turn-off, improvement of controllability of turn-off operation, and improvement of interruption capability at the time of turn-off.SOLUTION: A manufacturing method of a semiconductor device according to the present invention includes a step of activating first ions by first annealing to form a first buffer layer, a step of implanting second ions from the other main surface side of a semiconductor substrate to a position deeper than the first buffer layer from the other main surface, a step of activating the second ions by second annealing to form a second buffer layer having a maximum impurity concentration which is higher than an impurity concentration of a drift layer and is 1.0×10cmor less, a step of forming an active layer on the other main surface of the semiconductor substrate, and a step of forming a second electrode on the active layer, and the first annealing is performed before the step of implanting the second ions and the step of forming the active layer.SELECTED DRAWING: Figure 86
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Inventors:
Katsumitsu Nakamura
Application Number:
JP2020070948A
Publication Date:
September 22, 2021
Filing Date:
April 10, 2020
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/336; H01L21/329; H01L29/06; H01L29/12; H01L29/739; H01L29/78; H01L29/861; H01L29/868
Domestic Patent References:
| JP2013153183A |
Foreign References:
| WO2013141181A1 | ||||
| WO2016080288A1 | ||||
| WO2016147264A1 |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita