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Title:
METHOD FOR ARRANGING CHIP OF FIRST SUBSTRATE ON SECOND SUBSTRATE
Document Type and Number:
Japanese Patent JP2009076924
Kind Code:
A
Abstract:

To achieve the simultaneous examination of different chips of one substrate with increased economy.

A method for arranging the chips (102-110) of a first substrate (100) on a second substrate (111) is disclosed, in which the chips are grouped into at least first chips (102) and second chips (103), the first chips (102) of the first substrate (100) are individualized, and the individualized first chips (102) are arranged on the second substrate (111) in such a way that each of the first chips (102) on the second substrate (111) is unambiguously assigned to the associated first chip (102) on the first substrate (100).


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Inventors:
KERBER MARTIN
Application Number:
JP2008271440A
Publication Date:
April 09, 2009
Filing Date:
October 21, 2008
Export Citation:
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Assignee:
INFINEON TECHNOLOGIES AG
International Classes:
H01L21/66; G01R31/26; H01L23/52; H01L21/58; H01L21/78; H01L23/544; H01L25/065; H01L25/07; H01L25/18; H01L21/00
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita



 
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