Title:
MLSE EQUALIZER AND DEMODULATOR USING THE SAME
Document Type and Number:
Japanese Patent JP3629059
Kind Code:
B2
Abstract:
PURPOSE: To regenerate reception data and a burst reception signal without degrading the bit error rate characteristic of the reception signal by providing an MLSE equalizer capable of high-speed processing.
CONSTITUTION: A replica generation part 1, an error calculation part 2, a branch metric part 3, an addition, comparison, and selection processing part 4, an impulse response operation part 2, and a path memory part 6 have independent computing elements, and an impulse response memory part 7 is inserted to simultaneously execute the write of the operation result from the impulse response operation part 5 and the read of the operation result from the impulse response operation part 5 to a replica generation part 1. A pass metric memory part is provided to simultaneously execute the read of the pass metric at the preceding time and the write of the selected pass metric at the present time selected by the addition, comparison, and selection processing part 4.
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Inventors:
Yoshihiko Taki
Toshio Narita
Mitsuo Kobayashi
Ryoichi Minowa
Hiroyuki Onyanagi
Shingo Sakamoto
Unno Isamu
Kenetsu Furuki
Kenji Suzuki
Suzuki Tomoyuki
Toshio Narita
Mitsuo Kobayashi
Ryoichi Minowa
Hiroyuki Onyanagi
Shingo Sakamoto
Unno Isamu
Kenetsu Furuki
Kenji Suzuki
Suzuki Tomoyuki
Application Number:
JP7696495A
Publication Date:
March 16, 2005
Filing Date:
March 31, 1995
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03H21/00; H03M13/23; H04B3/04; H04B7/005; H04L27/01; H04L27/22; (IPC1-7): H04B7/005; H04L27/01; H04L27/22
Domestic Patent References:
| JP6338914A | ||||
| JP5316083A | ||||
| JP6224885A | ||||
| JP60190034A | ||||
| JP6232918A | ||||
| JP6120992A |
Attorney, Agent or Firm:
Yu Sanada
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