Title:
MULTIPROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS6194169
Kind Code:
A
Abstract:
PURPOSE:To improve the memory access efficiency of the whole of a device by providing two memory busses for one memory and connecting processors, between which information is transferred much, to the same bus. CONSTITUTION:Processors 11 and 12 are connected to a memory bus 31, and processors 13 and 14 are connected to a memory bus 32. Bus use right control circuits 61 and 62 control the use right of memory busses 31 and 32 and are connected to processors 11, 12, 13, and 14 and a bus switch circuit 5. The bus switch circuit 5 separates and connects memory busses 31 and 32 logically to switch information transfer between processors 11-14 and a memory 21.
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Inventors:
MARUYAMA MASATO
Application Number:
JP21449684A
Publication Date:
May 13, 1986
Filing Date:
October 13, 1984
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F12/00; G06F13/362; G06F13/40; G06F15/16; G06F15/177; (IPC1-7): G06F13/18; G06F15/16
Domestic Patent References:
| JPS5391645A | 1978-08-11 | |||
| JPS5680722A | 1981-07-02 | |||
| JPS56118127A | 1981-09-17 | |||
| JPS5748150A | 1982-03-19 |
Attorney, Agent or Firm:
Suzuki Makoto