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Title:
NON-VOLATILE SEMICONDUCTOR STORAGE
Document Type and Number:
Japanese Patent JP2002056699
Kind Code:
A
Abstract:

To solve such a problem that in a rewritable non-volatile semiconductor memory, it is hard to judge whether intended voltage is applied or not in various disturbance evaluations and tests, also a test time for evaluation and test of a block erasure function is increased as increment of the number of erasure blocks and rewriting stress for a memory cell at a test is increased.

This storage is provided with a memory cell 2 for monitoring, of which the control gate 3 is made common with a memory cell array 1 and in which a source and a drain can be controlled independently and electrical write-in and erasure can be performed, and at the time of evaluation and test, it is confirmed that intended voltage is surely applied by a function of simultaneous selection of plural word lines, a function of simultaneous selection of plural bit lines, and a function of simultaneous selection of source lines.


Inventors:
KOTANI HIDETO
Application Number:
JP2000243504A
Publication Date:
February 22, 2002
Filing Date:
August 11, 2000
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/3185; G11C16/04; G11C17/00; G11C29/00; G11C29/24; G01R31/28; (IPC1-7): G11C29/00; G01R31/28; G01R31/3185; G11C17/00; G11C16/04
Attorney, Agent or Firm:
Yoshihiro Morimoto