PURPOSE: To provide the phase synchronizing circuit which stabilizes the output signal while increasing the synchronizing speed.
CONSTITUTION: A feedback loop R1 is provided which is provided with a voltage controlled oscillator 22a whose frequency of the output signal is large changed based on the change of the analog voltage outputted from a loop filter 21a. A feedback loop R2 is provided which is provided with a voltage controlled oscillator 22b which is provided with input terminals Ti1 and Ti2 to which analog voltages are inputted and where the change of the frequency of the output signal due to the chan1e of the analog voltage inputted to the input terminal Ti2 is larger than that due to the change of the analog voltage inputted to the input terminal Ti1. The output signal of the loop filter 21b of the feedback loop R2 is inputted to the input terminal Ti1 of the voltage controlled oscillator 22b, and the output signal of the loop filter 21a of the first feedback loop R1 is inputted to the input terminal Ti2 of the voltage controlled oscillator 22b.
WO/2024/059587 | SINGLE AND DUAL EDGE TRIGGERED PHASE ERROR DETECTION |
JP4807909 | Phase-locked loop and phase-locked loop method |
JPH05183431 | PHASE LOCKED LOOP CIRCUIT |
YOSHIKAWA KIMIO
FUJITSU VLSI LTD
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