Title:
POLISHING METHOD
Document Type and Number:
Japanese Patent JP2001162524
Kind Code:
A
Abstract:
To prevent a semiconductor wafer from becoming a tapered shape and to improve the flatness of the semiconductor wafer.
Concerning a polishing condition, each number of revolutions of a sun gear 3, an internal gear 4, an upper surface plate 5 and a lower surface plate 6 is decided so as to fix the rotating direction of a semiconductor wafer 1, or each number of revolutions of the sun gear 3, the internal gear 4, the upper surface plate 5 and the low surface plate 6 is decided so as to fix a rotation moment direction applied on the semiconductor wafer 1.
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Inventors:
NAKAGAWA YASUTADA
Application Number:
JP35056499A
Publication Date:
June 19, 2001
Filing Date:
December 09, 1999
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
B24B7/17; B24B37/08; H01L21/304; (IPC1-7): B24B37/04; B24B7/17; H01L21/304
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)