PURPOSE: To simultaneously execute writing and reading for a next processing in the same instruction cycle.

CONSTITUTION: The memory cells of three transistors are used for a memory A cell 3 and a memory B cell 5. The write bit lines and read bit lines are made private and they are individually given. Namely, one vertical bit line is required at every processor element from an input SAM part to an ALU array part via a data memory part, while two vertical bit lines of the read bit line from the input SAM part to the ALU array part via the data memory A part and the write bit line from the ALU array part to the data memory A part are required at every processor in a conventional case. At that time, one transistor for writing and two transistors for reading in the memory A cell 3 are connected to the different write bit lines and the read bit lines.