REDUNDANCY PROGRAM CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

Japanese Patent JP2006019010

A

To provide a redundancy program circuit for a semiconductor memory device.

The redundancy program circuit is provided with a master fuse section which generates an operation enable signal to indicate presence or absence of a master fuse cutting, a control fuse section which generates first-M th control signal pairs (where M is a natural number≥2) indicating at least equal to 2 or more control fuse cuttings, a multiplexing section which outputs the logical states of half signal bits among a decoding address to the number of output terminals corresponding to the half signal bits in accordance with the corresponding control signal pairs among the control signal pairs and a second multiplexing section which transmits the logical state having one bit finally obtained to a program output terminal by subordinately reducing to one half of the half of the signal bits being outputted through the output terminal of a first multiplexing section in accordance with the residual control signal pairs that are not applied to the first multiplexing section among the control signal pairs when the operation enable signal is to be activated.

JPH0696598	SEMICONDUCTOR MEMORY AND DEFECTIVE MEMORY CELL RELIEVING CIRCUIT
JPH08297992	SEMICONDUCTOR MEMORY ELEMENT AND ITS DATA RECORDING METHOD

NAM JEONG-SIK
BOKU SHOKIN
KIM KWANG-HYUN
MOON BYUNG-SIK
JUNG WON-CHANG

JP2005193039A

January 19, 2006

June 30, 2005

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SAMSUNG ELECTRONICS CO LTD

G11C29/04

JP2005327432A	2005-11-24
JPH01224999A	1989-09-07
JP2001067891A	2001-03-16
JP2006172585A	2006-06-29
JPH10326496A	1998-12-08
JPH07153295A	1995-06-16
JP2000048593A	2000-02-18
JPH06259989A	1994-09-16
JPH04192198A	1992-07-10
JP2000048594A	2000-02-18

Makoto Hagiwara

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