PURPOSE: To contain a test circuit in a bulk including a logic cell and an array structure by constructing a switching transistor for use in testing a logic circuit with a transistor not used ordinarily.
CONSTITUTION: A plurality of first testing wirings 3 are provided along logic cells 2 arranged in the row direction of a logic cell array, and a plurality of second testing wirings 4 are provided along logic cells 2 arranged in the column direction of the logic cell array. Further, a switching transistor 5 is provided for each logic cell 2 located at an intersection between the first testing wiring 3 and the second testing wiring 4. The switching transistor 5 is formed with small transistors included in the logic cell 2. Hereby, there can be realized a semiconductor integrated circuit device including therein a test circuit with use of a bulk having the logic cells and the array structure, without newly providing any bulk and logic cells.
| JP2001345387 | I/O ARCHITECTURE FOR INTEGRATED CIRCUIT |
| JP2758727 | [Title of Invention] Semiconductor integrated circuit device |
| JPS60192346 | INTEGRATED CIRCUIT |
SHIKATANI JUNICHI
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