Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP4408500
Kind Code:
B2
Abstract:
A semiconductor integrated circuit according to the present invention comprises a memory array, an input circuit for writing data in the memory array and reading data from the memory array, an output circuit and a package, including 100 pins, storing the memory array, the input circuit and the output circuit. A fourth pin, an eleventh pin, a twentieth pin, a twenty-seventh pin, a fifty-fourth pin, a sixty-first pin, a seventieth pin and a seventy-seventh pin are supplied with the same voltage. The input circuit and the output circuit receive a power supply voltage from different ones of these pins. Thus, a semiconductor integrated circuit resistant against noise and capable of responding to a high operating frequency is provided.
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Inventors:
Shigeru Obayashi
Application Number:
JP32831499A
Publication Date:
February 03, 2010
Filing Date:
November 18, 1999
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C11/41; G11C11/413; H01L21/822; H01L21/8244; H01L23/50; H01L27/04; H01L27/11
Domestic Patent References:
| JP10326489A | ||||
| JP10294429A | ||||
| JP1258461A | ||||
| JP2000002750A | ||||
| JP11213664A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai