To realize the high speed of a writing rate without enlarging a chip size with respect to a semiconductor memory circuit (DRAM) which is provided with gate receiving type memory cell parts.

This memory circuit is provided with first and second MOS transistors N1, N2 whose gates are connected respectively to one pair of bit lines BT, BN which are to be connected to a memory cell MC and a sense amplifier SA and which are made to perform ON/OFF operations in accordance with levels of the bit lines, third and fourth MOS transistors N3, N4 which are inserted respectively between these MOS transistors N1, N2 and data busses DT, DN and which are made to perform an ON operation by a column switch signal YSW0 indicating that the bit lines are to be selected and fifth and sixth MOS transistors N5, N6 which are connected respectively between respective bit lines and the data busses and which are made to perform an ON operation based on the output of respective seventh and eighth MOS transistors N7, N8 ANDing a write signal WSW indicating to be a write and the column switch signal YSW0, and the circuit realizes the high speed of the writing rate by performing a write-in operation while connecting the bit lines and the data busses through these MOS transistors N5, N6.