Title:
フローティングボディ効果を除去した半導体メモリ素子及びその製造方法
Document Type and Number:
Japanese Patent JP4343460
Kind Code:
B2
Abstract:
A semiconductor memory device from which a floating body effect is eliminated and which has enhanced immunity to external noise, and a method of fabricating the same are provided. The memory device includes a semiconductor substrate. A plurality of bit lines are buried in the semiconductor substrate such that the surfaces of the bit lines are adjacent to the surface of the semiconductor substrate. The bit lines are arranged in parallel with one another. A plurality of word lines are formed on the semiconductor substrate so that the word lines cross and are isolated from the bit lines. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a body region including a vertical channel region and a second source/drain region which are formed sequentially on the bit line. The vertical access transistor contacts a gate insulation layer formed on a portion of one side of the sidewalls of the word line. Body regions including the channel regions of the access transistors are connected to one another to be a single integrated region.
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Inventors:
Kim Chang Hyun
Gold respect
Ryo Genjo
Gold respect
Ryo Genjo
Application Number:
JP2001177544A
Publication Date:
October 14, 2009
Filing Date:
June 12, 2001
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
H01L21/8242; C12S5/00; H01L27/108
Domestic Patent References:
| JP61140170A | ||||
| JP63263758A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Takashi Watanabe