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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS61217999
Kind Code:
A
Abstract:

PURPOSE: To use and select as two types of memories of an ECC circuit incorporating type of non-incorporated type by providing a means for selecting and controlling a function of the ECC circuit provided on a memory chip to a valid condition or to an invalid condition in accordance with the result detecting whether an ECC circuit selecting signal is impressed to an external terminal or not.

CONSTITUTION: There is provided an ECC circuit selecting signal detecting circuit 5 for detecting whether an ECC circuit selecting signal is impressed or not within a fixed period in an external terminal 1. There is provided an ECC function selecting control means 6 that in accordance with an output signal of this detecting circuit 5, a connecting condition of an ECC circuit and a memory circuit 3 is changed over and controlled to a valid or an invalid condition. As enbodiment of this selecting control means 6, a switch circuit for selecting and controlling the circuit connection of the ECC circuit 4 and the memory circuit 3 may be disposed, or a part of gates in the ECC circuit 4, for example, a parity inspection result data inputting AND gate 39 in a correction data producing circuit 37 may be changed so as to perform a gate control by an ECC function selecting control signal from the ECC circuit selecting signal detecting circuit 5.


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Inventors:
OSAWA TAKASHI
NATORI KENJI
Application Number:
JP5987985A
Publication Date:
September 27, 1986
Filing Date:
March 25, 1985
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F11/10; G06F11/08; G11C11/401; G11C29/00; G11C29/42; (IPC1-7): G06F11/08; G11C29/00
Domestic Patent References:
JP53071339B
JPS5496936A1979-07-31
JPS5332634A1978-03-28
Attorney, Agent or Firm:
Takehiko Suzue