Title:
半導体記憶装置および半導体記憶装置への書込み方法
Document Type and Number:
Japanese Patent JP6854714
Kind Code:
B2
Abstract:
To provide a semiconductor storage device and a writing method to a semiconductor storage device in which an error at the time of reading out data from a memory cell is suppressed even if an environmental condition changes, compared to a case where the write voltage is not corrected.SOLUTION: A semiconductor storage device comprises: a memory cell array composed of a plurality of memory cells; and a cell voltage generation unit that includes a high voltage generation unit which boosts a power supply voltage to generate a high voltage which is a cell voltage to be applied to each of the plurality of memory cells, a correction current generation unit which generates a correction current for correcting change of the cell voltage with respect to ambient temperature, and a control signal generation unit which compares a detected voltage obtained by converting the high voltage into current with the target current maintaining the high voltage at the target voltage to generate a control signal controlling a boosting operation in the high voltage generation unit, and adds a reference current which is the target current corresponding to the room temperature and the correction current to obtain the target current.SELECTED DRAWING: Figure 2
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Inventors:
Toshiro Sasaki
Application Number:
JP2017123744A
Publication Date:
April 07, 2021
Filing Date:
June 23, 2017
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
G11C16/30; G11C5/14; G11C7/04; G11C16/24
Domestic Patent References:
| JP2013212010A | ||||
| JP2012174315A | ||||
| JP201098050A |
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazunori
Hiroshi Fukuda
Kato Kazunori
Hiroshi Fukuda