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Patent Searching and Data


Title:
SIGNAL INPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH06237159
Kind Code:
A
Abstract:

PURPOSE: To attain stable circuit operation by providing a means detecting it that all signal lines go to H (all H) and a means letting an output of a latch-up circuit be an L level when all H is first detected by the detection means after application of power source and keeping the L state so as to shorten voltage level uncertainly time at the time of application of power source.

CONSTITUTION: Just after application of power source, since a signal at a point A produced by a resistor Rr, Cr and a Schmitt buffer 5 remains at an L level, the signal at the point A is inputted to a CLR of a D flip-flop 6 to let an output (signal at a point C) of the flip-flop 6 go to H and output levels of D0'-Dn' (signal input terminal 3) all go to H via an OR circuit 4. That is, just after application of power source, the level of the data buses D0'-Dn' is set to H. When the signal at the point A and the signals of D0-Dn all go to H, a signal at a point C goes to an L level. Thus, the signal levels of the D0-Dn go to the signal levels of the D0'-Dn' (signal input terminal 3) as they are.


Inventors:
MACHIMURA NORIYUKI
Application Number:
JP2382393A
Publication Date:
August 23, 1994
Filing Date:
February 12, 1993
Export Citation:
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Assignee:
SHARP KK
International Classes:
H03K17/22; H04L12/40; (IPC1-7): H03K17/22; H04L12/40
Attorney, Agent or Firm:
Hisao Komori