STATIC SEMICONDUCTOR MEMORY

Japanese Patent JP2004128239

A

To provide a static semiconductor memory which is excellent in soft-error tolerance by addition of a capacitance to a memory node.

A memory cell of the static semiconductor memory is provided with a gate electrode 2 of an MOS transistor which is formed on the principal plane of a semiconductor substrate 1 through an insulating film 3, an interlayer insulating film 4 covering the gate electrode 2, a pair of contact holes 9 provided in the interlayer insulating film 4 each reaching a source and a drain that are disposed at the opposite sides of the gate electrode 2, a plug portion 6 formed in each of the contact holes 9, and a metal wiring 7 formed on each of the plug portions 6. The distance S1 between the contact holes 9 positioned in the interlayer insulating film 4 is made smaller than a distance S2 between the contact holes 9 in the surface of the interlayer insulating film 4.

JP4539844	Dielectric capacitors and their manufacturing methods and semiconductor devices
JPH11283936	MANUFACTURE OF SEMICONDUCTOR DEVICE
JPS6235679	MANUFACTURE OF SEMICONDUCTOR DEVICE

IDEI MAKOTO
FUJII YASUHIRO

JP2002290801A

April 22, 2004

October 03, 2002

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RENESAS TECH CORP

H01L21/28; G11C11/41; H01L21/768; H01L21/8244; H01L23/485; H01L23/522; H01L27/10; H01L27/11; (IPC1-7): H01L21/8244; G11C11/41; H01L21/28; H01L21/768; H01L27/10; H01L27/11

Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai

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