PURPOSE: To obtain a switched capacitor circuit operated properly without increasing in power consumption and chip size even at the time of driving by low voltage by decreasing a threshold voltage of a CMOS switch so as to decrease its ON-resistance.

CONSTITUTION: When CMOS analog switches S1-S4 have a P-channel well in a switched capacitor circuit receiving an input voltage VIN to its input capacitive element C1 via the switches S1-S4 switched with a biphase clock signal whose level varied between a positive and a negative power supply voltage VDD and VSS, a well voltage VB is selected higher than the voltage VSS and when the switches S1-S4 have an N-channel well, the well voltage VB is selected lower than the voltage VDD and the well voltage is set in a range where no turn-on current is caused in an equivalent diode produced between the P-channel or N-channel well and the source. Through the constitution above, a sufficiently low on-resistance is obtained and desired low voltage driving is attained.