Title:
THIN-FILM MULTILAYER WIRING BOARD AND METHOD OF MANUFACTURING SAME
Document Type and Number:
Japanese Patent JP2010123904
Kind Code:
A
Abstract:
To provide a thin-film multilayer wiring board in which less peeling occurs, and a method of manufacturing the same.
The thin-film multilayer wiring board includes a first SiO2 thin film having at least one wiring layer formed on a lower wiring layer, an SiON thin film formed on the first SiO2 thin film, a second SiO2 thin film formed on the SiON thin film, a wiring conductor formed while buried in the second SiO2 thin film, a via conductor connecting with the wiring conductor and penetrating the first SiO2 thin film, SiON thin film, and second SiO2 thin film to electrically connect with the wiring conductor of the lower wiring layer, and an SiN thin film formed on the second SiO2 thin film.
More Like This:
| JP4000815 | Semiconductor device |
| JP2012248802 | MANUFACTURING METHOD OF ELECTRONIC MEMBER |
| WO/2010/108957 | METHOD FOR PRODUCING ELECTRICAL INTERCONNECTIONS MADE OF CARBON NANOTUBES |
Inventors:
FUKUSHIMA TAKEYUKI
SASAJIMA YUICHI
SASAJIMA YUICHI
Application Number:
JP2008298828A
Publication Date:
June 03, 2010
Filing Date:
November 21, 2008
Export Citation:
Assignee:
TAIYO YUDEN KK
International Classes:
H01L21/768; H01L21/312; H01L21/316; H01L21/318; H01L23/522