Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2900854
Kind Code:
B2
Abstract:
A semiconductor memory device comprises a plurality of sub-bit lines, a sense amplifier provided in common to the plurality of sub-bit lines and receiving a data signal from a first one of the plurality of sub-bit lines, a main-bit lines operatively coupled to the sense amplifier to receive an output of the sense amplifier, and a data latch circuit provided to latch data appearing on the main-bit line. The devices further comprises means for transferring a data signal of a second one of the plurality of sub-bit lines to the sense amplifier during the data latch circuit being accessed to read out data latched in the data latch circuit.
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Inventors:
SUGIBAYASHI NAOHIKO
NARITAKE ISAO
NARITAKE ISAO
Application Number:
JP23650895A
Publication Date:
June 02, 1999
Filing Date:
September 14, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G11C11/401; C21C5/40; G11C7/06; G11C7/18; G11C11/409; H01L21/8242; H01L27/108; (IPC1-7): G11C11/401; H01L21/8242; H01L27/108
Domestic Patent References:
| JP6203552A | ||||
| JP1138685A | ||||
| JP1138686A | ||||
| JP6275063A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)