PURPOSE: To obtain high speed information processing performance, by providing an operand supply function to a central processing unit so as to maximize the performance of a main storage independently of the storage location of an operand to the main storage device.

CONSTITUTION: The operand supply device 3 is provided with address registers 33, 37 representing addresses of the 1st and the 2nd operands in the main storage. Further, operand buffers 40, 43 storing temporarily the 1st and the 2nd operands are provided. The sequence of reading out the 1st and the 2nd operands from the device 1 is dependent on the head storage address of both the operands, and a sequence control circuit 50 generating a revision timing to each of the register 33, the buffer 40, the register 37 and the buffer 43 is provided. The order of access request for the readout of the device 3 is determined in advance so as not to produce collision between access requests in each bank in the device 1. The access request is generated according to the predetermined order.