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Title:
NON-VOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS59113594
Kind Code:
A
Abstract:

PURPOSE: To prevent the destruction of an internal element even if a high voltage impressed externally rises by providing a voltage limiting means to give a boosted voltage which is limited to a certain voltage or lower, to the gate of an insulated gate transistor (TR).

CONSTITUTION: Two enhancement MOSTRs 72 and 73 are inserted in series between a terminal 62 and the earth potential point, and the gate of the MOSTR72 on the side of the terminal 62 is connected to the terminal 62, and the gate of the MOSTR73 on the earth potential side is connected to the earth potential point, thus constituting a voltage control circuit 71. Even if a voltage VP rises as shown in Fig., a voltage VH of the terminal 62 which is the output terminal of a voltage boosting circuit does not rise over 25V, and consequently, a voltage VI does not exceed 22V. Therefore, even if the voltage VP rises to 26V because of noise or erroneous use, internal MOSTRs are not destructed.


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Inventors:
ASANO MASAMICHI
IWAHASHI HIROSHI
Application Number:
JP22415682A
Publication Date:
June 30, 1984
Filing Date:
December 21, 1982
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
G11C11/407; G11C16/02; G11C16/06; G11C17/00; (IPC1-7): G11C17/00
Domestic Patent References:
JPS56157262A1981-12-04
JPS5713143A1982-01-23
JPS58215793A1983-12-15
Attorney, Agent or Firm:
Takehiko Suzue