PURPOSE: To allow a clock cycle time to allow the writing cycle time of a memory cell and to prevent the generation of malfunction such as writing in a non-selected memory cell by providing the title circuit with a writing current detecting circuit, a coincidence circuit and a writing end circuit.

CONSTITUTION: The writing current detecting circuit W detects current flowing into a writing transistor (TR) group QW and converts the detected current into a voltage signal. The coincidence circuit C compares an output signal WA with a writing control signal WD and an output signal WB with a writing control signal, the inverse of WD, and when both the signals do not coincide with each other, turns its output signals CA, CB to a high level, and in case of coincidence, turns the signals CA, CB to a low level. The writing end circuit E is a logical NOR circuit between the output signals CA, CB and writing pulse signal, the inverse of WP, and generates a writing end signal WE and its emitter output is wired-OR connected with a writing pulse signal, the inverse of WP'. Since it is unnecessary to consider the dispersion of rise timing of the signal, the inverse of WP, the writing cycle time can be shortened. In addition, it is unnecessary to consider the generation of malfunction which may be generated in a RM integrated circuit when the writing pulse signal is kept at the low level for a long period.