Title:
BUFFER CIRCUIT AND IMAGING DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/024334
Kind Code:
A1
Abstract:
The present invention provides a buffer circuit that can achieve a wide dynamic range while maintaining a low output impedance, and with which reduced circuit area and low power consumption can be attained. The buffer circuit comprises a first transistor, a current source, a second transistor, an output terminal, and first and second capacitors. The first transistor has a gate that accepts the input of an input signal. The current source is connected to one terminal of the first transistor. The second transistor is connected to an other terminal of the first transistor. The output terminal is connected to the one or the other terminal of the first transistor. The first and second capacitors are provided between the current source and a gate of the second transistor. The first transistor, the second transistor, and the first capacitor form a first feedback circuit. The first transistor, the current source, and the second capacitor form a second feedback circuit.
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Inventors:
YAKUSHIJI YUKEN (JP)
Application Number:
PCT/JP2023/022641
Publication Date:
February 01, 2024
Filing Date:
June 19, 2023
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H04N25/78; H03F1/34; H03K19/0175
Domestic Patent References:
| WO2022030207A1 | 2022-02-10 |
Foreign References:
| JP2011091759A | 2011-05-06 | |||
| JP2016152495A | 2016-08-22 |
Attorney, Agent or Firm:
TANAKA Hidetetsu et al. (JP)
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