RESISTANCE DEVICE, INTEGRATED CIRCUIT DEVICE, IMPLANTABLE DEVICE, AND CORRECTION COEFFICIENT DETERMINING METHOD

Title:

RESISTANCE DEVICE, INTEGRATED CIRCUIT DEVICE, IMPLANTABLE DEVICE, AND CORRECTION COEFFICIENT DETERMINING METHOD

Document Type and Number:

WIPO Patent Application WO/2021/132084

Kind Code:

A1

Abstract:

This resistance device (100) comprises: a field effect transistor (TN); and a voltage application circuit (1). The voltage application circuit (1) applies, between the gate and the source of the field effect transistor (TN), a control voltage (Vgs) corresponding to a temperature (T), and controls the resistance value (R) between the drain and the source of the field effect transistor (TN). The control voltage (Vgs) indicates a voltage obtained by adding a correction voltage (Vc) to a reference voltage (Vgs0). The correction voltage (Vc) depends on the temperature (T) and is set to be zero at a first temperature (T1).

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Inventors:

KAMEDA SEIJI (JP)
HIRATA MASAYUKI (JP)

Application Number:

PCT/JP2020/047455

Publication Date:

July 01, 2021

Filing Date:

December 18, 2020

Export Citation:

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Assignee:

UNIV OSAKA (JP)

International Classes:

H01L27/04; G01K7/00; G05F1/567

Domestic Patent References:

WO2018147407A1

2018-08-16

Foreign References:

JP2011254408A	2011-12-15
JP2017534171A	2017-11-16
JP2015122635A	2015-07-02
JP2015122635A	2015-07-02

Other References:

C.A.MEAD: "Analog VLSI and Neural Systems", 1989, ADDISON-WESLEY PUBLISHING COMPANY
T. DELBRUCKC.A. MEAD: "Proceedings of IEEE International Symposium on Circuits and Systems", 1994, article "Adaptive photoreceptor with wide dynamic range"
See also references of EP 4084071A4

Attorney, Agent or Firm:

MAEI Hiroyuki (JP)

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