SEMICONDUCTOR DEFECT CLASSIFYING METHOD, SEMICONDUCTOR DEFECT CLASSIFYING APPARATUS, AND SEMICONDUCTOR DEFECT CLASSIFYING PROGRAM

WIPO Patent Application WO/2011/004534

A1

Disclosed is a semiconductor defect classifying method, wherein defects are efficiently and effectively classified by highly accurately determining the overlapping state of a design layout pattern and the defects, and systematic defects are easily identified. Semiconductor device defect images, which are obtained by means of defect inspection or defect review, and design layout data are automatically pattern-matched, and the defects are superimposed on the design layout pattern of at least one layer of a target layer, the upper layer of the target layer or the lower layer of the target layer. The overlapping states of the defects are determined by whether the defects are within the pattern, over the patterns or outside of the pattern, and the defects are automatically classified.

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HAYAKAWA KOICHI (JP)
HIRAI TAKEHIRO (JP)
TANDAI YUTAKA (JP)
ISHIKAWA TAMAO (JP)
SAKAI TSUNEHIRO (JP)
HASUMI KAZUHISA (JP)
NEMOTO KAZUNORI (JP)
ICHINOSE KATSUHIKO (JP)
TAKAGI YUJI (JP)

PCT/JP2010/003259

January 13, 2011

May 14, 2010

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HITACHI HIGH TECH CORP (JP)
HAYAKAWA KOICHI (JP)
HIRAI TAKEHIRO (JP)
TANDAI YUTAKA (JP)
ISHIKAWA TAMAO (JP)
SAKAI TSUNEHIRO (JP)
HASUMI KAZUHISA (JP)
NEMOTO KAZUNORI (JP)
ICHINOSE KATSUHIKO (JP)
TAKAGI YUJI (JP)

G01N21/956

JP2009010286A	2009-01-15
JP2003086645A	2003-03-20
JP2009516832A	2009-04-23

INOUE, MANABU (JP)
Manabu Inoue (JP)

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