Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2011/145240
Kind Code:
A1
Abstract:
A reference cell (C1) has gate patterns (G1, G2 and G3) extending in the Y direction and arranged at the same pitch in the X direction, and the terminal sections (e1, e2, e3) of the gate patterns (G1, G2 and G3) are in the same position in the Y direction and have equal widths in the X direction. A diode cell (C2) is adjacent to the reference cell (C1) in the Y direction. In addition to diffusion layers (D1 to D10) that function as diodes, the diode cell (C2) is provided with a plurality of opposing terminal sections (eo1, eo2 and eo3) which comprise gate patterns (G4, G5 and G6) and are arranged so as to oppose the terminal sections (e1, e2, e3).
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Inventors:
IKEGAMI TOMOAKI
NAKANISHI KAZUYUKI
TAMARU MASAKI
NAKANISHI KAZUYUKI
TAMARU MASAKI
Application Number:
PCT/JP2011/000927
Publication Date:
November 24, 2011
Filing Date:
February 18, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
IKEGAMI TOMOAKI
NAKANISHI KAZUYUKI
TAMARU MASAKI
IKEGAMI TOMOAKI
NAKANISHI KAZUYUKI
TAMARU MASAKI
International Classes:
H01L21/822; H01L21/82; H01L27/04
Domestic Patent References:
| WO2006118098A1 | 2006-11-09 |
Foreign References:
| JP2010021469A | 2010-01-28 | |||
| JP2006245390A | 2006-09-14 | |||
| JP2008235350A | 2008-10-02 | |||
| JP2007042718A | 2007-02-15 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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Claims:
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