Title:
SEMICONDUCTOR LAYOUT STRUCTURE AND SEMICONDUCTOR TEST STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2023/197400
Kind Code:
A1
Abstract:
The embodiments of the present disclosure relate to the technical field of semiconductors, in particular to a semiconductor layout structure and a semiconductor test structure. The semiconductor layout structure comprises: active layers, the active layers comprising a first active region and a second active region arranged adjacent to the first active region, the first active region comprising a plurality of first transistor regions arranged at intervals, the second active region comprising a plurality of second transistor regions arranged at intervals, and the active layers corresponding to the adjacent first transistor regions being separated from each other; and a gate layer, located above the active layers and comprising at least one first gate structure extending in a first direction and a plurality of second gate structures arranged at intervals in the first direction, the first gate structure and the second gate structures being adjacently arranged, the first gate structure corresponding to the first transistor regions, and the second gate structures corresponding to the second transistor regions.
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Inventors:
WANG XIANGYU (CN)
LI NING (CN)
LI NING (CN)
Application Number:
PCT/CN2022/093395
Publication Date:
October 19, 2023
Filing Date:
May 17, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L27/02; G01R31/26; H01L21/66; H01L23/544
Foreign References:
| CN1805139A | 2006-07-19 | |||
| CN111223854A | 2020-06-02 | |||
| CN206040637U | 2017-03-22 | |||
| CN101268541A | 2008-09-17 | |||
| CN112687664A | 2021-04-20 | |||
| CN105428271A | 2016-03-23 | |||
| CN106560909A | 2017-04-12 | |||
| US20030122160A1 | 2003-07-03 |
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
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