Title:
SEMICONDUCTOR STORAGE DEVICE USING STT-MRAM
Document Type and Number:
WIPO Patent Application WO/2015/083754
Kind Code:
A1
Abstract:
This STT-MRAM (100) contains a plurality of memory cells (50) and a sensing circuit (30) comprising an n-type MOSFET (30a) and an n-type MOSFET (30b). The drain of the n-type MOSFET (30a) is connected to one (BL) of a pair of bit lines, and the drain of the n-type MOSFET (30b) is connected to the other (BBL) of the pair of bit lines. The gate of the n-type MOSFET (30a) is connected to the drain of the n-type MOSFET (30b), and the gate of the n-type MOSFET (30b) is connected to the drain of the n-type MOSFET (30a). Each memory cell contains a pair of MTJs (10, 11) and a pair of p-type MOSFETs (20a, 20b) connected to a pair of source lines (SL, BSL).
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Inventors:
OHSAWA TAKASHI (JP)
ENDOH TETSUO (JP)
ENDOH TETSUO (JP)
Application Number:
PCT/JP2014/082040
Publication Date:
June 11, 2015
Filing Date:
December 03, 2014
Export Citation:
Assignee:
UNIV TOHOKU (JP)
International Classes:
G11C11/15
Foreign References:
| JP2011204287A | 2011-10-13 | |||
| JP2005518627A | 2005-06-23 | |||
| JP2002260377A | 2002-09-13 | |||
| JP5492324B1 | 2014-05-14 | |||
| US20130322161A1 | 2013-12-05 |
Attorney, Agent or Firm:
KIMURA MITSURU (JP)
Mitsuru Kimura (JP)
Mitsuru Kimura (JP)
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