MAGNETOELECTRIC PARA-ELECTRICS

BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (e.g., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than 100 mA/bit) and voltage

(e.g., greater than 0.7 V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the spin filtering tunneling dielectric of the MTJs e.g., magnesium oxide (MgO).

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates a magnetization response to an applied magnetic field for a ferromagnet.

[0005] Fig. IB illustrates a magnetization response to an applied magnetic field for a paramagnet.

[0006] Fig. 1C illustrates a magnetization response to an applied voltage field for a paramagnet connected to a magnetoelectric layer.

[0007] Fig. 2A illustrates a magnetoelectric spin orbit (MESO) logic with ferroelectric super lattice for magnetoelectric para-electrics, according to some embodiments of the disclosure. [0008] Fig. 2B illustrates a spin orbit material stack at the input of a charge interconnect, according to some embodiments of the disclosure.

[0009] Fig. 2C illustrates a magnetoelectric material stack at the output of a charge interconnect, according to some embodiments of the disclosure.

[0010] Fig. 3A illustrates a MESO logic with ferroelectric super lattice for magnetoelectric para-electrics and electrode with hexagonal material, according to some embodiments of the disclosure.

[0011] Fig. 3B illustrates a magnetoelectric material stack of the device of Fig. 3A at the output of a charge interconnect, according to some embodiments of the disclosure.

[0012] Figs 4A-D illustrate crystal or stacked hexagonal structures of magnetoelectric para-electric (e.g., Chromia), hexagonal manganite (e.g., YMnO), hexagonal ferromagnet super lattice, and hexagonal electrode (e.g., I Ch), respectively, according to some embodiments of the disclosure.

[0013] Fig. 5A illustrates a MESO logic of Fig. 2A which is operable as a repeater, according to some embodiments.

[0014] Fig. 5B illustrates a MESO logic of Fig. 2A which is operable as an inverter, according to some embodiments.

[0015] Fig. 6 illustrates a top view of a layout of the MESO logic of Fig. 2A, according to some embodiments.

[0016] Figs. 7A-B illustrate a ferroelectric Landau Khalatnikov (LK) model and corresponding plot showing two ferroelectric states.

[0017] Fig. 8 illustrates a majority gate using MESO logic devices of Fig. 2A, according to some embodiments.

[0018] Fig. 9 illustrates a flowchart of a method for forming a MESO logic device of

Fig. 2A and/or Fig. 3A, according to some embodiments of the disclosure.

[0019] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with the MESO logic, according to some embodiments.

DETAILED DESCRIPTION

[0020] The Magnetoelectric (ME) effect has the ability to manipulate the

magnetization (and the associated spin of electrons in the material) by an applied electric field. Since an estimated energy dissipation per unit area per magnet switching event through the ME effect is an order of magnitude smaller than with spin-transfer torque (STT) effect, ME materials have the capability for next-generation memory and logic applications. [0021] ME materials are generally divided into three categories. The first category of materials provide polarization and anti-feromagnetization. These materials include Bismuth ferrite (BFO), Lithium Iron Oxide (LFO) super lattice. The second category of materials also provide polarization and anti-feromagnetization, but at low temperatures. These materials include TbMnCri and similar multiferroic materials. The third category of materials are magnetoelectric para-electrics. These magnetoelectric para-electrics materials lack polarization, but provide anti-feromagnetization. The magnetoelectric para-electrics materials include chromia (CrcCh). Currently, MESO logic devices do not use chromia to provide ME effect because its material structure makes it incompatible with generally available magnets and conductors. The magnetoelectric para-electric materials (e.g., chromia) can provide additional stability to the MESO logic, provide directionality to the logic flow, and also provide small signals.

[0022] Various embodiments describe a MESO Logic which is a combination of various physical phenomena for spin-to-charge and charge-to-spin conversion, where the MESO logic comprises an input magnet and spin orbit coupling (SOC) structure having a stack of layers for spin-to-charge conversion. In some embodiments, spin-to-charge conversion is achieved via a layer with the inverse Rashba-Bychkov effect (or spin Hall effect) wherein a spin current injected from an input magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus by the direction of magnetization. In some embodiments, charge-to-spin conversion is achieved via magnetoelectric effect in which the charge current produces a voltage on a capacitor, comprising a layer with magnetoelectric effect, leading to switching magnetization of an output magnet. In some embodiments, magnetic response of a perpendicular magnet is through applied exchange bias from magnetoelectric effect. In some embodiments, a magnetoelectric oxide provides perpendicular exchange bias to the perpendicular magnet due to partially compensated anti-ferromagnetism.

[0023] The magnets of various embodiments are free magnets with hexagonal structure. Here, the term“hexagonal” generally refers to a lattice structure with atoms, ions, or molecules in a hexagonal formation. These magnets provide coupling compatibility with magnetoelectric para-electric materials, which also have hexagonal lattice structure. The ME material for the capacitor in various embodiments comprises magnetoelectric para-electric materials (e.g., chromia), which provides exchange bias to the hexagonal magnet. In some embodiments, the magnetoelectric para-electric material provides perpendicular polarization to the magnet. As such, in some embodiments, the magnets adjacent to the magnetoelectric para-electric material has perpendicular magnetic anisotropy (PMA) with magnetization perpendicular to the plane of the device having the MESO logic.

[0024] Compared to in-plane magnets, perpendicular magnets generally allow for easier lithography constraints on the magnetic dots with reduced aspect ratio requirements for shape. Perpendicular magnets (e.g., with out-of-plane magnetization) exhibit higher retention since the magnetic energy barrier is proportional to anisotropy.

[0025] In some embodiments, a ferroelectric (FE) material with hexagonal lattice structure is coupled to the magnetoelectric para-electric material to provide an interface with an electrode. In some embodiments, an electrode with hexagonal structure is coupled to the FE material. The hexagonal stack of materials (e.g., hexagonal magnet, hexagonal magnetoelectric para-electric, hexagonal manganite, and/or hexagonal electrode) enable the use of the third category of ME materials for MESO logic, in accordance with various embodiments.

[0026] There are many technical effects of various embodiments. For example, high speed operation of the logic (e.g., 100 picoseconds (ps)) is achieved via the use of magnetoelectric switching operating on semi-insulating nanomagnets. In some examples, switching energy is reduced (e.g., 1-10 attojoules (aJ)) because the current needs to be“on” for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor. In some examples, in contrast to the spin current, here charge current does not attenuate when it flows through an interconnect. The magnetoelectric para-electric based MESO logic provides an alternative to other types of MESO logics. Here, the magnetoelectric para-electric enables stability in the MESO logic operation and also provides small signal generation. Other technical effects will be evident from various embodiments and figures.

[0027] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0028] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0029] The term“free” or“unfixed” here with reference to a magnet refers to a magnet whose magnetization direction can change along its easy axis upon application of an external field or force (e.g., Oersted field, spin torque, etc.). Conversely, the term“fixed” or “pinned” here with reference to a magnet refers to a magnet whose magnetization direction is pinned or fixed along an axis and which may not change due to application of an external field (e.g., electrical field, Oersted field, spin torque,).

[0030] Here, perpendicularly magnetized magnet (or perpendicular magnet, or magnet with perpendicular magnetic anisotropy (PMA)) refers to a magnet having a magnetization which is substantially perpendicular to a plane of the magnet or a device. For example, a magnet with a magnetization which is in a z-direction in a range of 90 (or 270) degrees +/- 20 degrees relative to an x-y plane of a device.

[0031] Here, an in-plane magnet refers to a magnet that has magnetization in a direction substantially along the plane of the magnet. For example, a magnet with a magnetization which is in an x or y direction and is in a range of 0 (or 180 degrees) +/- 20 degrees relative to an x-y plane of a device.

[0032] The term“device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally a device is a three dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

[0033] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.

[0034] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.

[0035] The term“adjacent” here generally refers to a position of a thing being next to

(e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it). [0036] The term "circuit" or“module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

[0037] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0038] The term“scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term“scaling” generally also refers to downsizing layout and devices within the same technology node. The term“scaling” may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms “substantially,”“close,”“approximately,”“near, ” and“about,” generally refer to being within +/- 10% of a target value.

[0039] Unless otherwise specified the use of the ordinal adjectives“first,”“second,” and“third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0040] For the purposes of the present disclosure, phrases“A and/or B” and“A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0041] The terms“left,”“right,”“front,”“back,”“top,� �“bottom,”“over,”“under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0042] For the purposes of present disclosure, the terms“spin” and“magnetic moment” are used equivalently. More rigorously, the direction of the spin is opposite to that of the magnetic moment, and the charge of the particle is negative (such as in the case of electron).

[0043] It is pointed out that those elements of the figures having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0044] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term“MN” indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term“MP” indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0045] Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet (FM)

101. The plot shows magnetization response to an applied magnetic field for ferromagnet 101. The x-axis of plot 100 is magnetic field Ή’ while the y-axis is magnetization‘nf . For FM 101, the relationship between Ή’ and‘nf is not linear and results in a hysteresis loop as shown by curves 102 and 103. The maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturated magnetization configurations 104 and 106, FM 101 has stable magnetizations. In the zero magnetic field region 105 of the hysteresis loop, FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields. For example, the magnetization of FM 101 in configuration 105 can be either in the +y direction or the -y direction for an out-of-plane FM (e.g., FM with magnetization which is perpendicular to the plane of a device). As such, changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103.

[0046] Fig. IB illustrates magnetization plot 120 for paramagnet 121. Plot 120 shows the magnetization response to an applied magnetic field for paramagnet 121. The x-axis of plot 120 is magnetic field Ή’ while the y-axis is magnetization‘nf. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. Compared to plot 100, the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122. In the middle region 125, paramagnet 121 does not have any magnetization because there is no applied magnetic field (e.g., H=0). The intrinsic energy associated with switching is absent in this case.

[0047] Fig. 1C illustrates plot 130 showing magnetization response to applied voltage field for a paramagnet 131 connected to a magnetoelectric layer 132. Here, the x-axis is voltage‘V’ applied across ME layer 132 and y-axis is magnetization‘m\ Ferroelectric polarization‘PFE’ is in ME layer 132 is indicated by an arrow. In this example,

magnetization is driven by exchange bias exerted by a ME effect from ME layer 132. When positive voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the +y direction by voltage +V _C ) as shown by configuration 136.

When negative voltage is applied by ME layer 132, paramagnet 131 establishes a

deterministic magnetization (e.g., in the -y direction by voltage -V _c ) as shown by

configuration 134. Plot 130 shows that magnetization functions l33a and l33b have hysteresis. In some embodiments, by combining ME layer 132 with paramagnet 131, switching speeds of paramagnet as shown in Fig. IB are achieved. In some embodiments, the hysteresis behavior of FM 131, as shown in Fig. 1C, is associated with the driving force of switching rather than the intrinsic resistance of the magnet to switching.

[0048] Fig. 2A illustrates a magnetoelectric spin orbit (MESO) logic 200 with ferroelectric super lattice for magnetoelectric para-electrics, according to some embodiments of the disclosure. Fig. 2C illustrates a magnetoelectric material stack at the output of a charge interconnect, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 2A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0049] In some embodiments, MESO logic 200 comprises a first magnet 201, a spin- orbit coupling structure having a stack of layers (e.g., layers 202, 203, and 204, also labeled as 202a/b, 203a/b, and 204a/b), interconnecting conductor 205 (e.g., a non-magnetic charge conductor), magnetoelectric (ME) para-electric structure 206 (206a/b), second magnet 207, first contact 209a, second contact 209b, and ferroelectric (FE) material 212 (e.g., 2l2a/b).

[0050] In some embodiments, the first and second magnets 201 and 207, respectively, have perpendicular magnetic anisotropy (PMA). For example, first and second magnets 201 and 207, respectively, are free conducting magnets with perpendicular magnetization along the z-axis with reference to an x-y plane of a device having MESO logic 200. In various embodiments, to enable ME para-electric structure 206, first and second magnets 201 and 207, respectively, have hexagonal lattice structure. In some embodiments, first and second magnets 201 and 207, respectively, comprise oxides of Fe or oxides of Co. For example, Fe2Cb, Fe304, C02O3, or C02O4 can be used for forming first and second magnets 201 and 207, respectively. In some embodiments, first and second magnets 201 and 207, respectively, are a super lattice. For instance, a stack of materials such as Fe203 followed by alternating layers of LuFe204, LuFeCb, LuFe204, LuFeCb, and so on are used to form the super lattice.

As such, a hexagonal magnet with perpendicular magnetization is formed which enables the use of ME para-electric structure 206 that exerts perpendicular polarization.

[0051] In some embodiments, first magnet 201 comprises first and second portions, wherein the first portion of first magnet 201 is adjacent to the SOC structure having stack of layers (e.g., layers 202a, 203a, and 204a), and wherein the second portion of first magnet 201 is adjacent to ME para-electric structure 206b. In some embodiments, second magnet 207 comprises first and second portions, wherein the first portion of second magnet 207 is adjacent to the ME para-electric structure 206a, and wherein the second portion of second magnet 207 is adjacent to another SOC structure having a stack of layers (e.g., layers 202b, 203b, and 204b).

[0052] In some embodiments, conductor 205 (or charge interconnect) is coupled to at least a portion of the SOC structure having a stack of layers (e.g., one of layers 202a, 203a, or 204a) and FE material 2l2b. For example, conductor 205 is coupled to layer 204a of the stack.

[0053] In some embodiments, the stack of layers is to provide an inverse Rashba-

Bychkov effect (or inverse spin Hall effect). In some embodiments, the stack of layers provide spin-to-charge conversion where a spin current J _s or is injected from first magnet 201 (also referred to as the input magnet) and charge current I _c is generated by the stack of layers. This charge current L· is provided to conductor 205 (e.g., charge interconnect). In contrast to spin current, charge current does not attenuate in conductor 205. The direction of the charge current Ic depends on the direction of magnetization of first magnet 201. In some embodiments, the charge current Ic charges the capacitor around ME layer 206 and switches its polarization. ME magnetoelectric para-electrics 206 exerts exchange bias on second magnet layer 207, and the direction of the exchange bias determines the magnetization of second magnet 207.

[0054] In some embodiments, the charge current Ic charges the capacitor around ME para-electric structure 206a and switches its polarization. ME para-electric structure 206a exerts exchange bias on second magnet layer 207, and the direction of the exchange bias determines the magnetization of second magnet 207. The same dynamics occurs by ME para-electric structure 206b which exerts exchange bias on first magnet 201 according to input charge current on conductor 21 la.

[0055] In this example, the length of first magnet 201 is L _m , the width of conductor

205 is W _c , the length of conductor 205 from the interface of layer 204a to ME para-electric structure 206a is L _c , t _c is the thickness of the magnets 201 and 207, and ΪME is the thickness of ME para-electric structure 206a. In some embodiments, conductor 205 comprises a material including one of: Cu, Ag, Al, Au, Co, or Graphene.

[0056] In some embodiments, the input and output charge conductors (21 la and

21 lb, respectively) and associated spin-to-charge and charge-to-spin converters are provided. In some embodiments, input charge current Icharge(iN) (or IIN) is provided on interconnect 21 la (e.g., charge interconnect made of same material as interconnect 205). In some

embodiments, interconnect 21 la is coupled to first magnet 201 via ME para-electric structure 206b. In some embodiments, interconnect 21 la is orthogonal to first magnet 201. For example, interconnect 21 la extends in the +x direction while first magnet 201 extends in the -y direction. In some embodiments, Icharge(iN) is converted to corresponding magnetic polarization of 201 by ME para-electric structure 206b. The materials for ME para-electric structure 206a/b are the same as the materials of ME para-electric structure 206.

[0057] In some embodiments, an output interconnect 21 lb is provided to transfer output charge current Idiarge(OUT) to another logic or stage. In some embodiments, the output interconnect 21 lb is coupled to second magnet 207 via a stack of layers that exhibit spin Hall effect and/or Rashba-Bychkov effect. For example, layers 202b, 203b, and 204b are provided as a stack to couple output interconnect 21 lb with second magnet 207. Material wise, layers 202b, 203b, and 204b are formed of the same material as layers 202a, 203a, and 204a, respectively.

[0058] In some embodiments, ME para-electric structure 206a/b forms the magnetoelectric capacitor to switch the magnets 201/207. For example, conductor 205 forms one plate of the capacitor, magnet 207 forms the other plate of the capacitor, and layer 206a is the magnetic-electric oxide that provides an out-of-plane exchange bias to second magnet 207. In some embodiments, the magnetoelectric oxide comprises perpendicular exchange bias due to partially compensated anti-ferromagnetism.

[0059] In some embodiments, first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202a, 203a, and 204a). The spin polarization is determined by the magnetization of first magnet. [0060] In some embodiments, the stack comprises i) an interface 203a/b with a high density 2D (two dimensional) electron gas and with high SOC formed between 202a/b and 204a/b materials such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt.

[0061] In some embodiments, the stack of layers providing spin orbit coupling comprises: a first layer 202a/b comprising Ag, wherein the first layer is adjacent to first magnet 209a/b; and a second layer 204a/b comprising Bi or W, wherein second layer 204a/b is adjacent to first layer 202a/b and to a conductor (e.g., 205, 21 lb). In some embodiments, a third layer 203a/b (having material which is one or more of Ta, W, or Pt) is sandwiched between first layer 202a/b and second layer 204a/b as shown. In some embodiments, the stack of layers comprises a material which includes one of: b-Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[0062] In some embodiments, the 2D materials include one or more of: Mo, S, W, Se,

Graphene, M0S2, \VSe2. WS2, or MoSe2. In some embodiments, the 2D materials include an absorbent which includes one or more of: Cu, Ag, Pt, Bi, Fr, or H absorbents. In some embodiments, the SOC structures comprise a spin orbit material which includes materials that exhibit Rashba-Bychkov effect. In some embodiments, material which includes materials that exhibit Rashba-Bychkov effect comprises materials ROCI12, where‘R’ includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where“Ch” is a chalcogenide which includes one or more of: S, Se, or Te.

[0063] In some embodiments, a spacer (or template layer) is formed between the first magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 201. In some embodiments, the metal of the spacer, which is directly coupled to first magnet 201, is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table. In some embodiments, first magnet 201 (and by extension first semi -insulating magnet 209a) are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).

[0064] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant‘a’ within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (i.e., matching gets closer to perfect matching), spin injection efficiency from spin transfer from first magnet 201 to first ISHE/ISOC stacked layer increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device.

[0065] In some embodiments, a transistor (e.g., p-type transistor MP1) is coupled to first conducting magnet 201 via contact 209a (e.g., Cu, Al, Ag, or Au, etc.). In this example, the source terminal of MP1 is coupled to a supply Vdd, the gate terminal of MP1 is coupled to a control voltage Vd (e.g., a switching clock signal, which switches between Vdd and ground), and the drain terminal of MP1 is coupled to first magnet 201 via contact 209a. In some embodiments, contact 209a is made of any suitable conducting material is used to connect the transistor to the first magnet 201. In some embodiments, the current Id c from transistor MP1 generates spin current into the stack of layers (e.g., layers 202a, 203a, and 204a).

[0066] In some embodiments, along with the p-type transistor MP1 connected to Vdd

(or an n-type transistor connected to Vdd but with gate overdrive above Vdd), an n-type transistor MN1 is provided which couples to first magnet 201 via contact 209a, where the n- type transistor is operable to couple ground (or 0 V) to first magnet 201. In some

embodiments, an n-type transistor MN2 is provided which is operable to couple ground (or 0V) to second magnet 207 via contact 209b.

[0067] In some embodiments, a p-type transistor MP2 is provided which is operable to couple power supply (Vdd or -Vdd) to second conducting magnet 207 via contact 209b. For example, when clock is low (e.g., Vd=0 V), then transistor MP1 is on and Vdd is coupled to first conducting magnet 201 (e.g., power supply is Vdd) and 0V is coupled to second conducting magnet 207. This provides a potential difference for charge current to flow. Continuing with this example, when clock is high (e.g., Vd=Vdd and power supply is Vdd), then transistor MP1 is off, transistor MN1 is on, and transistor MN2 is off. As such, 0 V is coupled to first conducting magnet 201.

[0068] In some embodiments, the power supply is a negative power supply (e.g., -

Vdd). In that case, then transistor MPl’s source is connected to 0 V, and transistor MNl’s source is connected to -Vdd, and transistor MN2 is on. When Vd = 0 V and power supply is - Vdd , then transistor MN1 is on, and transistor MP1 is off, and transistor MN2 (whose source is at -Vdd ) is off and MP2 whose source is 0 V is on. In this case, -Vdd is coupled to input magnet 201 and 0 V is coupled to output magnet 207 via respective contacts 209a/b. This also provides a path for charge current to flow. Continuing with this example, when the clock is high (e.g., Vd=-Vdd and power supply is -Vdd), then transistor MP1 is off, transistor MN1 is on, and transistor MN2 is off. As such, 0 V is coupled to input magnet 201.

[0069] Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion

[0070] In some embodiments, the spin-orbit mechanism responsible for spin-to- charge current conversion is described by the inverse Rashba-Bychkov effect in a 2D electron gases. Positive currents along the +y axis produce a spin injection current with transport direction along the +z direction and spins pointing to the +z direction.

Js ^xvz Jy Ά

[0071] The Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:

HR = a _R (k x x). s

where a _R is the Rashba coefficient,‘k’ is the operator of momentum of electrons, x is a unit vector along the gradient of the potential at the surface, and s is the operator of spin of electrons. This results in the generation of a charge current P in interconnect 205 proportional to the spin current (or J _s ). The spin-orbit interaction by Ag and Bi interface layers (e.g., the Inverse Rashba-Bychkov Effect (IRBE)) produces a charge current P in the horizontal direction given as:

where w _m is width of the input magnet 201, and l _IKUE is the IRYE constant (with units of length) proportional to a _R .

[0072] IRBE effect produces spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width. The net conversion of the drive charge current Idrtve to magnetization dependent charge current is given as:

where‘P’ is the dimensionless spin polarization. For this estimate, the drive current /,/,·«- (Id) and the P signal charge current I _c = I _d = 100 mA is set. Estimating the resistance of the ISHE interface to be equal to R = 100 W, then the induced voltage is equal to V _ISHE = 10 mV.

[0073] The charge current I _c , carried by interconnect 205, produces a voltage on the capacitor of ME para-electrics structure 206 comprising magnetoelectric material dielectric in contact with second magnet 207 (which serves as one of the plates of the capacitor). In some embodiments, magnetoelectric materials are either intrinsic multiferroics or composite multiferroic structures that have para-electric properties. As the charge accumulates on the magnetoelectric capacitor of ME para-electrics structure 206, a strong magnetoelectric interaction causes the switching of magnetization in second magnet 207. For the following parameters of the magnetoelectric capacitor: thickness t _ME = 5 nm, dielectric constants = 500, area A = 60 nm x 20 nm. Then the capacitance is given as:

ee _h A

C = « IfF

^ME

[0074] Demonstrated values of the magnetoelectric coefficient is a _ME ~10/c , where the speed of light is c. This translates to the effective magnetic field exerted on the nanomagnets, which is expressed as:

BME = a _ME E = ^aMEVlSHE -0.06 T

tME

This is a strong field sufficient to switch magnetization.

[0075] The charge on the capacitor of ME para-electrics structure 206 is Q =

1

— x 10 mV = 10 aC. and the time to fully charge it to the induced voltage is the induced voltage is td = 10 Q/I _d ~l ps (with the account of decreased voltage difference as the capacitor charges). If the driving voltage is V _d = 100 mV. then the energy E _sw to switch is expressed as:

£ _sw ~100 mV x 100 mA x 1 ps~10 aj

which is comparable to the switching energy of CMOS transistors. Note that the time to switch t _sw magnetization remains much longer than the charging time and is determined by the magnetization precession rate. The micro-magnetic simulations predict this time to be t _sw ~100 ps, for example. In some embodiments, a non-magnetic electrode (e.g., Cu) is formed and coupled to layer 204 to provide a connection to a supply (e.g., ground or Vdd). In some embodiments, the sideways section of conducting interconnect 205 is aligned with the interface between layer 202 and 204 to capture sideways IRBE current. [0076] In some embodiments, materials for the first and second magnets 201 and 207 have saturated magnetization M _s and effective anisotropy field Hk. Saturated magnetization Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Anisotropy Hk generally refers material properties that are highly directionally dependent.

[0077] In some embodiments, materials for first and second magnets 201 and 207, respectively, are non-ferromagnetic elements with strong paramagnetism which have a high number of unpaired spins but are not room temperature ferromagnets. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. In some embodiments, magnets 201 and 207 comprise paramagnets with hexagonal lattice structure.

[0078] The paramagnet can include one or more of: Platinum(Pt), Palladium (Pd),

Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnCh (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy ₂ 0 (dysprosium oxide), Erbium (Er), EnCh (Erbium oxide), Europium (Eu), EmC (Europium oxide), Gadolinium (Gd), Gadolinium oxide (GdrCh). FeO and Fe ₂ C>3 (Iron oxide), Neodymium (Nd), Nd ₂ 0 ₃ (Neodymium oxide), K0 ₂ (potassium superoxide), praseodymium (Pr), Samarium (Sm), SrmCh (samarium oxide), Terbium (Tb), TbrCh (Terbium oxide), Thulium (Tm), TrmCh (Thulium oxide), or V ₂ 03 (Vanadium oxide). In some embodiments, the first and second paramagnets 201 and 207 comprise dopants selected from a group which includes one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.

[0079] In some embodiments, ME para-electric structure 206a/b is formed of a material which includes one of: Cr ₂ 03 or another multiferroic material. In some

embodiments, ME para-electric structure 206 comprises Cr and O. In some embodiments, FE layer or structure 212 (e.g., 2l2a/b) comprises a hexagonal manganite RMnCh, where‘R’ is one of Sc, Y, Dy, Ho, Er, Tm, Yb, or Lu. The lattice structure of this material substantially or completely matches with the hexagonal structure of ME para-electric structure 206a/b.

This FE structure allows the integration of ME para-electric structure 206a/b to a conductor such as conductors 21 la and 205.

[0080] Fig. 3A illustrates a MESO logic 300 with ferroelectric super lattice for magnetoelectric para-electrics and electrode with hexagonal material, according to some embodiments of the disclosure. Fig. 3B illustrates a magnetoelectric material stack of Fig.

3A at the output of a charge interconnect, according to some embodiments of the disclosure. MESO logic 300 is similar to MESO logic 200 except for electrode 213 (e.g., 2l3a/b) which is adjacent to FE layer 212 (e.g., 2l2a/b) and conductor (e.g., 205, 21 la). In some embodiments, electrode 2l3a/b also has a hexagonal structure so that it seamlessly interfaces with the hexagonal manganite of structure 2l2a/b. In some embodiments, electrode 2l3a/b comprises indium, tin, and oxygen (e.g., IroCri) which provides a hexagonal template for hexagonal manganite of structure 2l2a/b. For example, ImCb has approximately 1 % lattice mismatch to the hexagonal manganite, and also has a resistivity of approximately 10 ⁴ Ohm. Centimeter. Another example of a hexagonal ferroelectric used for making electrode 2l3a/b includes InGa03. Technical effect wise, MESO logic 300 functions and operates same as MESO logic 200.

[0081] Figs 4A-D illustrate crystal or stacked hexagonal structures of magnetoelectric para-electric (e.g., Chromia) 400 (e.g., used for structure 206a/b), hexagonal manganite 420 such as RMn03 (e.g., used for structure 2l2a/a/b), hexagonal ferromagnet super lattice 430 (e.g., used for magnets 201 and/or 207), and hexagonal electrode 440 such as I Cri or InGa03 electrode (e.g., used for electrode 2l3a/b), respectively, according to some embodiments of the disclosure. In some embodiments, hexagonal ferromagnet super lattice 430 comprises oxides of Fe or oxides of Co. These oxides are also referred to as conducting oxides. For example, Fe ₂ 03, Fe304, C02O3, or C02O4 can be used for forming first and second magnets 201 and 207, respectively. In various embodiments, the conducting oxides are hexagonal conducting oxides and/or doped hexagonal conducting oxides. For example, ZnO lattice matched to the ferroelectric material In203, InGaCh and the like. In some embodiments, first and second magnets 201 and 207, respectively, are a super lattice. For instance, a stack of materials such as layer 431 (e.g., FeiCh) followed by alternating layers of 432i-n and 433i- _n (e.g., LuFe204, LuFeCh, LuFe204, LuFeCb, and so on) are used to form the super lattice, where‘n’ is an integer. As such, a hexagonal magnet with perpendicular magnetization is formed which enables the use of ME para-electric structure 206 that exerts perpendicular polarization.

[0082] Fig. 5A illustrates a MESO logic 500 of Fig. 2A which is operable as a repeater, according to some embodiments. In some embodiments, to configure the MESO logic as a repeater, a portion of the stack of the layers (e.g., layer 204) is coupled to ground, first magnet 201 (input magnet) is coupled to a negative supply (e.g., -Vdd), and second magnet 207 (output magnet) is coupled to ground (e.g., 0V). For -Vdd supply voltage applied to the input magnet, a spin current polarized in the same direction as the nanomagnets is injected into the high SOC region (e.g., stack having layers 202, 203, and 204). The inverse Rashba-Bychkov effects (or inverse SOC effects of stack having layers 202, 203, and 204) produce a charge current proportional to the injected spin current. The injected charge current /c charges magnetoelectric stack (e.g., ME para-electric structure 206) producing a large effect magnetic field on output magnet 207. When SOL device 500 operates as a repeater, magnetization of input magnet 201 is same as the magnetization of output magnet 207.

[0083] Fig. 5B illustrates a MESO logic 520 of Fig. 2A which is operable as an inverter, according to some embodiments. In some embodiments, a portion of the stack of the layers (e.g., layer 204) is coupled to ground, first magnet 201 (input magnet) is coupled to a positive supply (e.g., +Vdd), and second magnet 207 (output magnet) is coupled to ground (e.g., 0V). The logic inverter operation of SOL device 520 works by injection of a spin current from input magnet 201 with a +Vdd supply voltage. The inverse Rashba-Bychkov effects (or SOC effects of stack having layers 202, 203, and 204) produces charge current Ic which is injected into conductor 205. The injected charge current Ic charges magnetoelectric stack including layer 206 with opposite polarity, producing a large effective magnetic field on the detector free layer 207. When MESO logic 520 operates as an inverter, magnetization of input magnet 201 is opposite to the magnetization of output magnet 207.

[0084] MESO devices of some embodiments provide logic cascadability and unidirectional signal propagation (e.g., input-output isolation). In some examples, the unidirectional nature of logic is ensured due to large difference in impedance for injection path versus detection path. The injector is essentially a metallic spin valve with spin to charge transduction with RA (resistance area) products of approximately 10 mOhm. micron ² . The detection path is a low leakage capacitance with RA products much larger than 1 MOhm. micron ² in series with the resistance of the FM capacitor plate with estimated resistance greater than 500 Ohms.

[0085] Fig. 6 illustrates a top view 600 of a layout of the MESO logic of Fig. 2A, according to some embodiments. An integration scheme for SOL devices with CMOS drivers for power supply and clocking is shown in the top view. Here, transistor MP1 is formed in the active region 601, and power supply is provided via metal layer 3 (M3) indicated as 606. The gate terminal 604 of transistor MP1 is coupled to a supply interconnect 605 through via or contact 603. In some embodiments, M3 layer 607 is coupled to ground which provides ground supply to layer 204. In some embodiments, another transistor can be formed in active region 802 with gate terminal 610. Here, 608 and 609 are contact vias to the power supply line. The density of integration of the devices exceeds that of CMOS since an inverter operation can be achieved within 2.5P x 2M0. In some embodiments, since the power transistor MP1 can be shared among all the devices at the same clock phases, vertical integration can also be used to increase the logic density.

[0086] Figs. 7A-B illustrate a ferroelectric Landau Khalatnikov (LK) model 700 and corresponding plot 720 showing two ferroelectric states. In some embodiments, positive polarization charge +QF corresponds to state‘ 1’ of the magnet, while negative polarization charge -QF corresponds to state‘0’ of the magnet. Here, normalized +QF(l) and -QF(-l) are used in circuit simulation to indicate the ferroelectric states. In some embodiments, model 700 captures the behavior of hexagonal manganite structure 212 and/or the behavior of ME para-electric structure 206.

[0087] LK model 700 illustrates a circuit that provides ferroelectric voltage VFE and comprises capacitor CO in parallel with a series coupled resistance p and internal capacitance CF(QFE) that provides internal voltage Vint. Here,‘A’ is the area of capacitor CO,‘d’ is the distance between the plates of capacitor CO, and E0 is the dielectric constant. Plot 720 shows the capacitance behavior of a ferroelectric capacitor (FE-Cap) when connected with a load capacitor. Here, x-axis is the internal voltage Vint in volts, while the y-axis is charge from the ferroelectric capacitor when connected with a load capacitor. The dotted region in plot 720 represents the negative capacitance region between the coercive voltage bounds.

[0088] When a voltage source drives the FE-Cap connected with a load capacitor, the operating region of a FE-cap is biased by the load capacitance. When the FE-Cap is biased at the negative capacitance region (e.g., charge on FE-cap is positive while the voltage across the FE-cap is negative, and vice versa), the voltage across the load capacitance can be higher than the input voltage, owning to the ferroelectric polarity charge induced voltage amplification effect. On the other hand, when the FE-Cap is biased at the positive capacitance region, it operates as a regular capacitor. The negative capacitance effect has been mainly utilized for transistor gate stack enhancement (e.g., negative capacitance FETs) for low-voltage transistors. Some embodiments use the concept of negative capacitance to a MESO logic to enhance the switching of magnets via the magnetoelectric layer.

[0089] Fig. 8 illustrates a majority gate 800 using MESO logic devices of Fig. 2A, according to some embodiments. A charge mediated majority gate is proposed using the spin orbit coupling and magnetoelectric switching. A charge mediated majority gate is shown in Fig. 8. Majority gate 800 comprises at least three input stages 801, 802, and 803 with their respective conductors 2051, 2052. and 2053 coupled to summing interconnect 904. In some embodiments, summing interconnect 804 (e.g., made of the same materials as interconnect 205). In some embodiments, summing interconnect 804 is coupled to the output stage 805 which includes the second magnet 207. The three input stages 801, 802, and 803 share a common power/clock region therefore the power/clock gating transistor can be shared among the three inputs of the majority gate, in accordance with some embodiments. The input stages 801, 802, and 803 can also be stacked vertically to improve the logic density, in accordance with some embodiments. The charge current at the output (Icharge(ouT)) is the sum of currents Idu, Idu, and Ido.

[0090] Fig. 9 illustrates a flowchart 900 of a method for forming a MESO logic device of Fig. 2A and/or Fig. 3A, according to some embodiments of the disclosure. While the blocks and/or operations are illustrated in a certain order, the order can be altered. For example, some blocks can be performed before or after others, and some can be performed simultaneously with others.

[0091] At block 901, a magnet (e.g., magnet 201/207) is formed having a first portion and a second portion. In some embodiments, the magnet has perpendicular magnetic anisotropy with magnetization pointing along a direction perpendicular to a plane of a device in the apparatus. In some embodiments, forming the magnet comprises forming a material with hexagonal lattice. In some embodiments, the magnet includes one or more of: Fe, Co, or O. In some embodiments, the magnet comprises oxides of Fe or Co. In some embodiments, forming the magnet comprises forming a super lattice of first material and a second material, wherein the first and second materials include one or more of: Lu, Fe, and O.

[0092] At block 902, a first structure is formed, a portion of which is adjacent to the first portion of the magnet, wherein the first structure is to provide an inverse spin orbit coupling effect. In some embodiments, forming the first structure comprises forming a material which includes one or more of: b-Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table group. In some embodiments, the stack of layers comprise materials ROG12, where R includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where Ch is a chalcogenide which includes one or more of: S, Se, or Te.

[0093] At block 903, a second structure is formed adjacent to the second portion of the magnet, wherein the second structure comprises a hexagonal material with

magnetoelectric properties. In some embodiments, the second structure includes Cr and O.

In various embodiments, the second structure exhibits magnetoelectric properties without residual polarization. One such material is chromia, for example. [0094] At block 904, a third structure is formed adjacent to the second structure, wherein the third structure comprises a hexagonal material. In some embodiments, the third material includes a hexagonal manganite. In some embodiments, the third material includes Y, Mn, and O.

[0095] At block 905, a fourth structure is formed adjacent to the third structure, wherein the fourth structure is substantially lattice matched to the third structure. In some embodiments, the fourth structure is formed adjacent to the third structure, wherein the fourth structure is substantially lattice matched to the third structure. In some embodiments, the fourth structure comprises a material which includes In and O. In some embodiments, the method comprises: forming a first conductor adjacent to the third structure; and forming a second conductor adjacent to a portion of the first structure.

[0096] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with the MESO logic having a ferroelectric super lattice for magnetoelectric para- electrics, according to some embodiments. Fig. 10 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0097] In some embodiments, computing device 1600 includes first processor 1610 with MESO logic having a ferroelectric super lattice for magnetoelectric para-electrics, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a MESO logic with ferroelectric super lattice for magnetoelectric para-electrics, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0098] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0099] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[00100] In some embodiments, computing device 1600 comprises display subsystem 1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[00101] In some embodiments, computing device 1600 comprises I/O controller 1640. I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[00102] As mentioned above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[00103] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[00104] In some embodiments, computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[00105] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[00106] In some embodiments, computing device 1600 comprises connectivity 1670. Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices. [00107] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00108] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00109] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00110] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00111] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00112] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00113] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00114] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00115] Example 1. An apparatus comprising: a magnet having a first portion and a second portion; a first structure, a portion of which is adjacent to the first portion of the magnet, wherein the first structure is to provide an inverse spin orbit coupling effect; a second structure adjacent to the second portion, the second structure comprising a material having a hexagonal structure with magnetoelectric properties; and a third structure adjacent to the second structure, the third structure comprising a material having a hexagonal structure. [00116] Example 2. The apparatus of example 1 comprises a fourth structure adjacent to the third structure, wherein the fourth structure is substantially lattice matched to the third structure.

[00117] Example 3. The apparatus of example 2, wherein the fourth structure comprises a material which includes: In and O; or In, Ga, and O.

[00118] Example 4. The apparatus according to any one of the preceding examples, wherein the magnet has perpendicular magnetic anisotropy with magnetization pointing along a direction perpendicular to a plane of a device in the apparatus.

[00119] Example 5. The apparatus according to any one of the preceding examples, wherein the magnet comprises a material with hexagonal lattice.

[00120] Example 6. The apparatus according to any one of the preceding examples, wherein the magnet includes one or more of: Fe, Zn, Co, or O.

[00121] Example 7. The apparatus according to any one of the preceding examples, wherein the magnet comprises oxides of Fe, Zn, or Co.

[00122] Example 8. The apparatus according to any one of the preceding examples, wherein the magnet comprises a super lattice of first material and a second material, and wherein the first and second materials include one or more of: Lu, Fe, and O.

[00123] Example 9. The apparatus according to any one of the preceding examples, wherein the first structure comprises a material which includes one or more of: b-Ta, b-W,

W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table group, or materials ROG12, where R includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where Ch is a chalcogenide which includes one or more of: S, Se, or Te.

[00124] Example 10. The apparatus according to any one of the preceding examples, wherein the second structure includes: Cr and O.

[00125] Example 11. The apparatus according to any one of the preceding examples, wherein the third material includes a hexagonal manganite RMnCh, where‘R’ is one of Sc,

Y, Dy, Ho, Er, Tm, Yb, or Lu.

[00126] Example 12. The apparatus according to any one of examples 1 to 10, wherein the third material includes Sc, Y, Dy, Ho, Er, Tm, Yb, or Lu, Mn, and O.

[00127] Example 13. The apparatus of example 1 comprises: a first conductor adjacent to the third structure; and a second conductor adjacent to a portion of the first structure. [00128] Example 14. An apparatus comprising: a first device comprising an apparatus according to any one of examples 1 to 13, wherein the second conductor of the first device is to provide a first input charge current; a second device comprising an apparatus according to any one of examples 1 to 13, wherein the second conductor of the second device is to provide a second input charge current; a third device comprising an apparatus according to any one of examples 1 to 13; wherein the second conductor of the third device is to provide a third input charge current; a third conductor coupled to the first conductors of first, second, and third devices; and a fourth device comprising an apparatus according to any one of examples 1 to 13, wherein the second conductor of the fourth device is coupled to the third conductor; and a fourth conductor coupled to the first conductor of the fourth device.

[00129] Example 15. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of examples 1 to 12 or an apparatus according to example 14; and wireless interface to allow the processor to communicate with another device.

[00130] Example 16. A method comprising: forming a magnet having a first portion and a second portion; forming a first structure, a portion of which is adjacent to the first portion of the magnet, wherein the first structure is to provide an inverse spin orbit coupling effect; forming a second structure adjacent to the second portion, the second structure comprising a material having a hexagonal structure with magnetoelectric properties; and forming a third structure adjacent to the second structure, the third structure comprising a material having a hexagonal structure.

[00131] Example 17. The method of example 16 comprises forming a fourth structure adjacent to the third structure, wherein the fourth structure is substantially lattice matched to the third structure.

[00132] Example 18. The method of example 17, wherein the fourth structure comprises a material which includes In and O.

[00133] Example 19. The method according to any one of the preceding method examples, wherein the magnet has perpendicular magnetic anisotropy with magnetization pointing along a direction perpendicular to a plane of a device in the apparatus.

[00134] Example 20. The method according to any one of the preceding method examples, wherein forming the magnet comprises forming a material with hexagonal lattice.

[00135] Example 21. The method according to any one of the preceding method examples, wherein the magnet includes one or more of: Fe, Zn, Co, or O. [00136] Example 22. The method according to any one of the preceding method examples, wherein the magnet comprises oxides of Zn, Fe or Co.

[00137] Example 23. The method according to any one of the preceding method examples, wherein forming the magnet comprises forming a super lattice of first material and a second material, wherein the first and second materials include one or more of: Lu, Fe, and O.

[00138] Example 24. The method according to any one of the preceding method examples, wherein forming the first structure comprises forming a material which includes one or more of: b-Ta, b-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table group, or materials ROCh ₂ , where R includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where Ch is a chalcogenide which includes one or more of: S, Se, or Te.

[00139] Example 25. The method according to any one of the preceding method examples, wherein the second structure includes Cr and O.

[00140] Example 26. The method according to any one of the preceding method examples, wherein the third material includes a hexagonal manganite RMnCh, where‘R’ is one of Sc, Y, Dy, Ho, Er, Tm, Yb, or Lu.

[00141] Example 27. The method according to any one of the preceding method examples, wherein the third material includes Sc, Y, Dy, Ho, Er, Tm, Yb, or Lu, Mn, and O.

[00142] Example 28. The method of example 16 comprises: forming a first conductor adjacent to the third structure; and forming a second conductor adjacent to a portion of the first structure.

[00143] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.