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WO/1993/017381A1 |
A system performs dynamic segmentation analysis of attributes of a linear network, when the attributes are stored in a computer readable relational database. An embodiment of the system has an arrangement for converting data in the relat...
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WO/1993/014456A1 |
A barrel shifter capable of shifting input data in both directions, left and right, without increasing its circuit scale. In a barrel shifter unit circuit of a plural-stage barrel shifter, provided are a tristate buffer (11X) for left-sh...
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WO/1993/012481A2 |
A data buffer that compensates the differences in data rates, between a storage device and an image compression processor. A method and apparatus for the real time indexing of frames in a video data sequence.
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WO/1993/012600A1 |
A digital clock dejitter circuit includes a RAM (20) for receiving an incoming gapped signal (14a), a digital, fractional RAM fullness gauge (30) for tracking the average input and output rates to and from the RAM and for generating ther...
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WO/1992/022141A1 |
A series of data processors (20a-20n) operate on a body of data to convert it to compressed form for storage or transmission. The processors are connected in series such that the output of one processor is the input to the next processor...
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WO/1992/020176A1 |
A method of and apparatus for allocating memory for storage of vocabularies used in adaptive data compression of a frame-multiplexed data stream of a data communications network. More specifically, a memory (Fig.1, VA; Fig.3, 40) of a da...
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WO/1992/020028A1 |
Communication controller (3), for buffering data packets, interfaceable with a host processor (1) and a communication medium control unit (2) employing packet numbers assignment storing in a transmit queue (9) and a receive queue (10). E...
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WO/1992/017023A1 |
An information processing methodology gives rise to an application program interface which includes an automated digitizing unit, such as a scanner (210), which inputs information from a diversity of hard copy documents and stores inform...
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WO/1992/015159A1 |
An apparatus and method for clock rate matching in independent networks is disclosed. The apparatus accepts data from a modem (126) into a buffer (400) and determines the difference between the rate of the data entering the buffer (400) ...
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WO/1992/015055A1 |
Disclosed is a circuit designed to connect a microprocessor system (MP) to a communications channel (K) for series data transmission, the circuit ensuring optimum data transmission. This is done by the use of two first-in/first-out memor...
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WO/1992/010035A1 |
Improved means and methods are provided for transmitting binary data on a communication system, such as E-mail, which restricts the number of acceptable characters that can be transmitted. In a preferred embodiment, the binary data to be...
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WO/1992/009032A1 |
A bit disposal apparatus includes a register (16) which is divided at a truncation point (14) into a left register segment (18) and a right register segment (28), wherein bits to be disposed of are contained in the right register segment...
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WO/1992/008192A1 |
A system is provided including a host processor and an audio capture and playback adapter having a DSP co-processor. The adapter includes shared memory accessible from both the DSP and the host. A DSP program is periodically written to t...
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WO/1992/008304A1 |
An apparatus which receives a gapped data component of an STS-1 signal and provides therefrom an ungapped DS-3 data signal is provided and includes a FIFO (20) for receiving the data component (12) of the STS-1 signal, a measuring circui...
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WO/1992/008186A1 |
The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one...
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WO/1992/002999A1 |
An apparatus and method for transferring a data payload (SPE) from a first substantially SONET signal into a second substantially SONET signal of different frequency. A circuit (43a) for extracting the SPE bytes from the first SONET sign...
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WO/1992/002018A1 |
A method and apparatus are disclosed for storing and accessing information of both asynchronous and synchronous devices using, for example, pointers (62, 76) having grey code counters which reduce code conversion logic and which are less...
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WO/1991/018346A1 |
A device for transmitting a synchronous data which transmits data asynchronously from a first system controller to a second system controller. Transferred data is doubly stored in a first and a second memory. The data outputted from the ...
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WO/1991/013396A1 |
A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architectur...
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WO/1991/013398A1 |
A digital storage device is provided that includes a storage unit (12) having a plurality of word storage locations (14), each of the word storage locations being coupled to a corresponding read enable line (R) and write enable line (W),...
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WO/1991/013397A1 |
A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.
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WO/1991/010955A1 |
The invention relates to an address processor for a signal processor. This address processor comprises means for address calculation in a read/write memory containing at least one circular buffer for storing state variables of digital fi...
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WO/1991/011058A1 |
A method and apparatus is disclosed for providing modulation or compression encoding and decoding. A decoder effectuates a direct enumeration algorithm to accomplish a mapping and includes a ROM (1204) for receiving a signal representing...
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WO/1991/010999A1 |
A method for compressing user data for storing on tape (10) comprising the steps of: receiving a stream of user data words organised into a plurality of records (CRn); compressing the user data according to a compression algorithm involv...
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WO/1991/011000A1 |
A method for compressing user data for storing on tape (10) comprising the steps of: receiving a stream of user data words organised into a plurality of records (Rn); compressing the user data according to a compression algorithm involvi...
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WO/1991/007830A1 |
Clock dejitter circuits are provided and comprise control circuits (30) for generating a plurality of pulses over a clock cycle, and clock circuits (60) for tracking the speeds of jittered incoming data signal and based on those speeds, ...
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WO/1991/003880A1 |
The improved data compression system (100) concurrently processes both strings of repeated characters and textual substitution of input character strings. In this system (100), the performance of data compression techniques based on text...
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WO/1990/016025A2 |
Apparatus for connecting an additional data storage device to a computer port, such as a printer port, that is not necessarily adapted for connection to a data storage device. An interface circuit comprises means for reading stored multi...
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WO/1990/015385A1 |
A multiport register set (50) has an eight deep addressable stack (52) of N-bit wide data words (54). The stack (52) has a port (56) at the bottom of the stack and a port (58) at the top of the stack. A read counter (59) is connected by ...
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WO/1990/013866A1 |
The circuit includes a cascaded array of digital circuit blocks that together implement a matrix multiplication in each channel of a color video signal processing system. Each circuit block includes two registers for multiplying or divid...
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WO/1990/012360A1 |
The invention relates mainly to a device and a process for writing in a stack-type memory device. The invention concerns the use of stacks (1) of the first in, first out (FIFO) type to unscramble television images. In order to write into...
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WO/1990/010903A1 |
The serial data receiving circuit of the invention comprises a most significant bit input detecting circuit (20) which produces a predetermined control signal in synchronism with the reception of the most significant bit of serial data o...
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WO/1990/007184A1 |
A method and apparatus are disclosed for the handling of high speed data. In one mode of operation, the data is routed to a plurality of memory arrays (12, 14, 16, 18). In order to provide for the handling of a continuous stream of data ...
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WO/1990/006560A1 |
In a data compression system including a dynamically compiled dictionary the dictionary is updated by storing a string comprising a word and a part-word. The part-word comprises a plurality of characters from the string immediately follo...
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WO/1990/005364A1 |
A RAM-BASED FIFO (101) which provides self-timing of the data outputs (9, 18) in read mode. When the data output is not valid, the data output drivers are in a high-impedance condition. Therefore, FIFOs using this RAM-based architecture ...
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WO/1990/004294A1 |
A parallel asynchronous elasticity buffer. Selection of the address of a storage element for writing or reading of data is provided by asynchronous input and output pointers implemented using circular gray code counters. The buffer is in...
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WO/1990/000837A1 |
Data compression and decompression utilising e.g. the Ziv-Lempel algorithm is simplified by utilising a tree structure for the dictionary in which alternative symbols at a given position in a symbol sequence (a, b, c) are linked by linki...
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WO/1989/012866A1 |
An improved intermediate spreadsheet structure for representing n-dimensional spreadsheets as a set of nested segments. Each non-empty cell of the spreadsheet is represented by a cell segment (1617). Cells belonging to a first-dimensiona...
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WO/1989/012363A2 |
A data compression/decompression apparatus employs common circuitry and a single string table for compression and decompression. A throttle control is provided to prevent data under-runs and an optimizing start-up control delays the star...
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WO/1989/009439A1 |
The disclosure is directed to a serial in, serial out data shifter. Generally, the data shifter comprises a latch based design (L1-L4) with a four phase clock system (CLK1-CLK4). The latches (L1-L4) are coupled in series and the four pha...
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WO/1989/009441A1 |
The invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction. The apparatus and method employ: a low precision...
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WO/1989/007372A1 |
Variable length codewords are grouped into successive N bit word groups (25) in sequential order as received from a variable length codeword encoder (18). The N-bit groups are each stored in corresponding N-bit-wide memory locations in a...
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WO/1989/006014A1 |
A digital, intelligent memory chip (305, 306) is described that multiplies a matrix times a vector. It stores one or more bits of each element of a large matrix in a high capacity, many-column memory (400) that is on the chip, and multip...
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WO/1989/002127A1 |
A bus adapter connecting a high-speed pended bus (25) to a slower speed non-pended bus (45) includes a first module (69) functioning as a node of the pended bus and a second module (61) functioning as a node of the non-pended bus. An int...
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WO/1989/001668A1 |
The elements (36, 38, 40) of a transform processing circuit (30) are switchable to change the order of data in a data stream and/or to perform a fast Fourier transform (FFT) or inverse fast Fourier transform (IFFT) on the data stream. Ea...
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WO/1988/010466A1 |
When power is on and a system floppy (14, 15) is in a disc drive (11e), loading firmware (F1) reads the system program name from a predetermined memory region of the system floppy. Based on said system program name, the firmware checks w...
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WO/1988/008606A1 |
An apparatus having a mantissa part register and an index part register which transfers floating point data only is now permitted to input and output fixed point data, too. The registers are connected to individual inputs and outputs and...
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WO/1988/007297A1 |
Asynchronous time division communication system wherein user stations (US1/2), each with an associated send and receive circuit (SEND1/2, REC1/2), are coupled with a packet switching network (PSN). Each send circuit includes a send clock...
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WO/1988/003679A2 |
A data buffer/switch box comprising a plurality of input/output interface cards (10) removably connected to a motherboard, the data buffer/switch box including circuitry for a plurality of different interface cards provided on the mother...
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WO/1988/003681A1 |
A pipeline control system in which processing modules (1, 2, 3) and queues (4, 5) are connected in series. The respective processing modules are provided with interrupt control circuits (21, 22, 23). When the processing module (2) transf...
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