| Document |
Document Title |
|
WO/2021/126373A1 |
A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of a...
|
|
WO/2021/126917A1 |
Described herein are apparatuses and methods for applying high voltage, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., using a high voltage (e.g., MOSFET) gate driver circuit ...
|
|
WO/2021/122138A1 |
A duty cycle correction circuit comprises a buffer stage (120) which outputs a digital output signal (VOUT_RX) having a duty cycle. At least one buffer (125) of the buffer stage (120) is configured to exhibit a controllable tripping thre...
|
|
WO/2021/116434A1 |
An oscillator arrangement is provided, comprising a relaxation oscillator (2) having an active state and an inactive state; a bias current circuit portion (16) arranged to provide a bias current (14) to the relaxation oscillator (2) duri...
|
|
WO/2021/116263A1 |
A method serves for operating a drive unit comprising an active element (1) having a resonator (2) and an excitation means (23) for exciting oscillations in the resonator (2) and thereby driving a passive element (4). The method comprise...
|
|
WO/2021/112717A1 |
The invention relates to technology for producing high-voltage shock current pulses for non-lethal contact electroshock weapons and long-range electroshock weapons, and also to general technology for producing high-voltage high-current p...
|
|
WO/2021/110607A1 |
The present invention relates to a pulse generating circuit for an electrosurgical generator, for generating a waveform suitable for causing electroporation of biological tissue. The pulse generating circuit comprises a voltage source co...
|
|
WO/2021/110605A1 |
The present invention relates to a bipolar pulse generating circuit for an electrosurgical generator, for generating a waveform suitable for causing electroporation of biological tissue. The bipolar pulse generating circuit comprises a v...
|
|
WO/2021/111772A1 |
This comparator circuit outputs an output voltage at a first logic level if an input voltage exceeds a first threshold voltage, and outputs the output voltage at a second logic level if the input voltage falls below a second threshold vo...
|
|
WO/2021/107974A1 |
An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75V. The improved level shifter comprises a coupling stage and a level-switching ...
|
|
WO/2021/102927A1 |
Disclosed is a clock generation circuit, comprising a multi-phase clock generation circuit, an FM, a PD and a control circuit, wherein the multi-phase clock generation circuit is used for generating a multi-phase clock signal according t...
|
|
WO/2021/104093A1 |
A control circuit and a control method for a pulse output source, and a corresponding pulse source system. The control circuit comprises a trigger part, a cascade charging and discharging part, and a load part. The cascade charging and d...
|
|
WO/2021/097799A1 |
A duty cycle calibration circuit 10. The circuit comprises: a first phase inverter 101, a first delayer 102 and a first adjustment circuit 103, wherein an input end of the first phase inverter 101 is used for receiving a first signal, an...
|
|
WO/2021/100329A1 |
[Problem] To provide a voltage control device that makes it possible to maintain the power supply voltage of a controlled circuit at a voltage equal to or greater than a minimum operating voltage while remaining as close as possible to t...
|
|
WO/2021/086872A1 |
Devices, methods and techniques are disclosed for providing a multi-layer diode without voids between layers. In one example aspect, a multi-stack diode includes at least two Drift Step Recovery Diodes (DSRDs). Each DSRD comprises a firs...
|
|
WO/2021/080671A1 |
An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle r...
|
|
WO/2021/075150A1 |
The present invention provides a filter circuit capable of preventing, by a simple configuration, the circuit from malfunctioning even when power-supply voltage has changed, and a semiconductor device. This filter circuit is provided wit...
|
|
WO/2021/071426A1 |
A circuit for mitigating single-effect-transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to generate a first output and a first n-type transistor arrangement configured to gener...
|
|
WO/2021/067255A1 |
Described herein are apparatuses and methods for applying high voltage, high current, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., while preventing damage from load arcing. ...
|
|
WO/2021/059013A1 |
Methods and systems for classical processing in a quantum controller are operable to receive data from a quantum processor and demodulate a feedback pulse according to a command, a vector of digital samples and a vector of quadrature ref...
|
|
WO/2021/059579A1 |
The present invention comprises: a first wiring (11); a second wiring (12) that is not connected to the first wiring (11) and is provided for redundancy, to transmit the same signal level as the first wiring (11); and other wiring (21, 2...
|
|
WO/2021/059582A1 |
This semiconductor device comprises: a first latch circuit (L1) including a first inverting circuit (i1), a second inverting circuit (i2), a third inverting circuit (i3), and a fourth inverting circuit (i4); first-type well regions (Wp1,...
|
|
WO/2021/059580A1 |
A semiconductor device according to one embodiment of the present disclosure is provided with a plurality of wiring layers (M1 to M3), a first wiring line (11), and a second wiring line (12) which is not connected to the first wiring lin...
|
|
WO/2021/061170A1 |
An SEU immune flip-flop includes a master stage data latch, being transparent in response to a clock signal first state and being latched in response to a clock signal second state; a slave stage data latch; and a scan slave latch having...
|
|
WO/2021/062223A1 |
Some embodiments include a nonlinear transmission line system comprising: a power supply providing voltages greater than 100 V; a high frequency switch electrically coupled with the power supply; a nonlinear transmission line electricall...
|
|
WO/2021/059003A1 |
Method for generating gigahertz bursts of laser pulses is provided, where: 1) time delay T2 of the delayed part with respect to the undelayed part of the input pulse is longer than a time period T1 between said input pulse and the next i...
|
|
WO/2021/055155A1 |
A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an ...
|
|
WO/2021/044212A1 |
A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a con...
|
|
WO/2021/036071A1 |
Disclosed in embodiments of the present invention are a pulse signal generation device and method. The device comprises a clock module, an FPGA module and a control module. The clock module is used to provide a reference clock signal to ...
|
|
WO/2021/040947A1 |
A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver...
|
|
WO/2021/040594A1 |
Disclosed is a Radio Frequency communication device, RF communication device, (10) wherein said RF communication device (10) comprises a signal transmitting circuitry comprising tunnel diode oscillator circuitry, TDO circuitry, (13) and ...
|
|
WO/2021/035002A1 |
A comparator circuit includes a first transistor (206), a second transistor (208), a first switch (210), a second switch (212), and a timing circuit. The first transistor (206) and the second transistor (208) are coupled as a differentia...
|
|
WO/2021/029905A1 |
An improved level shifter for use in integrated circuits is disclosed. The level shifter is able to achieve a switching time below 1 ns while still using the core power supply voltages, VDDL and VDDH, used in the prior art. The improved ...
|
|
WO/2021/023129A1 |
A real-time pulse monitoring circuit (520) and a tumor treatment apparatus, the real-time pulse monitoring circuit (520) comprising a capacitor group (111), a pulse generator (320) connected to the positive pole of the capacitor group (1...
|
|
WO/2021/026499A1 |
An apparatus may include an energy rate limiter, an electro-optical transmitter, and an energy monitor. The energy rate limiter limits energy transfer, based on an energy control signal, from a power supply to the energy storage module. ...
|
|
WO/2021/023544A1 |
The invention relates to an optical pulse generator and to a method for operating an optical pulse generator. In particular, an optical pulse generator according to the invention is to uniformly supply all emitters and their segments of ...
|
|
WO/2021/025821A1 |
A latch and/or flip-flop with reduced dynamic capacitance for the clock node. Power associated with the clock node is reduced without timing impact. Merely two clock devices and merely the signal on the clock input pin toggles when the d...
|
|
WO/2021/023506A1 |
The present invention relates an implantable pulse generator comprising an electric circuit, wherein the electric circuit comprises: a primary energy store, at least one secondary energy store, and a control unit, wherein the control uni...
|
|
WO/2021/024083A1 |
The present invention provides a semiconductor device with a novel structure. The present invention has a CPU and an accelerator. The accelerator has a first memory circuit and a computation circuit. The first memory circuit has a first ...
|
|
WO/2021/021398A1 |
One example includes a superconducting clock conditioning system. The system includes a plurality of inductive stages. Each of the plurality of inductive stages includes an inductive signal path that includes at least one inductor and a ...
|
|
WO/2021/019542A1 |
A switching circuit comprises a main switch element having a gate as a control input; and a ring oscillator connected as a driver circuit to the gate to drive the main switch via the gate. The basic circuit is used to build various compo...
|
|
WO/2021/014891A1 |
Provided are a resonator, an oscillator, and a quantum computer capable of suppressing the occupied area of a circuit while achieving both moderate non-linearity and low loss. A resonator (100) comprises: at least one loop circuit (110) ...
|
|
WO/2021/016455A1 |
An electronic circuit (200) which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gat...
|
|
WO/2021/005439A1 |
Provided are novel oscillator, amplifier circuit, inverter circuit, amplifier circuit, battery control circuit, battery protection circuit, electrical storage device, semiconductor device, electrical equipment, and the like. This semicon...
|
|
WO/2021/000064A1 |
Disclosed in embodiments of the present application is an RC oscillator. The RC oscillator may use a first amplifier and a second amplifier to amplify the difference between a first voltage and a second voltage. The first amplifier may c...
|
|
WO/2021/003319A1 |
Some embodiments include a plasma system that includes a plasma chamber; an RF driver driving RF bursts into the plasma chamber with an RF frequency greater than 2 MFiz; a nanosecond pulser driving pulses into the plasma chamber with a p...
|
|
WO/2021/001040A1 |
An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4), connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) having its g...
|
|
WO/2020/262771A1 |
The present invention is formed so that a plurality of delay cells provide square-wave voltages to a plurality of transistors in accordance with specific time periods, the plurality of transistors transfer current to an oscillator in acc...
|
|
WO/2020/258640A1 |
An avalanche triode-based nanosecond pulse power supply for micro electric discharge machining, comprising: a direct current power supply (V1), a charging circuit, a discharging circuit, a driving pulse input circuit, and a steepening wa...
|
|
WO/2020/249922A1 |
Various implementations described herein are directed to a device having a voltage regulator that uses a modulator to adjust an output voltage. The device may include a time-to-digital converter that measures a timing delay of a logic ch...
|
