【発明の名称】信号パス遅延を減少させたカラム冗長回路

Title:

【発明の名称】信号パス遅延を減少させたカラム冗長回路

Document Type and Number:

Japanese Patent JP2002529874

Kind Code:

A

Abstract:

A semiconductor memory has memory elements arranged in memory blocks with each memory block having normal columns and at least one redundant column. In the event of a normal column being found to be defective, a redundant column may be used to replace the defective column. The semiconductor memory allows a redundant column in one block to replace a defective column in another block. The memory block may also be separated into an upper and lower portion allowing the portions to individually replace upper or lower column portions from different defective columns.

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Inventors:

Way, funsin
Hirohito Kikukawa
Ma, Cynthia

Application Number:

JP2000580093A

Publication Date:

September 10, 2002

Filing Date:

October 29, 1999

Export Citation:

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Assignee:

Mosside Technologies, Inc.
Matsushita Electric Industrial Co., Ltd

International Classes:

G11C11/401; G06F11/20; G11C29/00; G11C29/04; (IPC1-7): G11C29/00; G11C11/401

Domestic Patent References:

JPH01125799A	1989-05-18
JP2564507B2	1996-12-18
JP2000030485A	2000-01-28

Attorney, Agent or Firm:

Kenichi Oki

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